From: Kyrylo Tkachov Date: Wed, 31 May 2023 16:43:20 +0000 (+0100) Subject: aarch64: PR target/99195 Annotate saturating mult patterns for vec-concat-zero X-Git-Tag: basepoints/gcc-15~8692 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=547d3bce0c02dbcbb6f62d9469a71eedf17bd688;p=thirdparty%2Fgcc.git aarch64: PR target/99195 Annotate saturating mult patterns for vec-concat-zero This patch goes through the various alphabet soup saturating multiplication patterns, including those in TARGET_RDMA and annotates them with . Many other patterns are widening and always write the full 128-bit vectors so this annotation doesn't apply to them. Nothing out of the ordinary in this patch. Bootstrapped and tested on aarch64-none-linux and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_sqdmulh): Rename to... (aarch64_sqdmulh): ... This. (aarch64_sqdmulh_n): Rename to... (aarch64_sqdmulh_n): ... This. (aarch64_sqdmulh_lane): Rename to... (aarch64_sqdmulh_lane): ... This. (aarch64_sqdmulh_laneq): Rename to... (aarch64_sqdmulh_laneq): ... This. (aarch64_sqrdmlh): Rename to... (aarch64_sqrdmlh): ... This. (aarch64_sqrdmlh_lane): Rename to... (aarch64_sqrdmlh_lane): ... This. (aarch64_sqrdmlh_laneq): Rename to... (aarch64_sqrdmlh_laneq): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add tests for qdmulh, qrdmulh. * gcc.target/aarch64/simd/pr99195_10.c: New test. --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 2cd8b82df0fb..1efae8d5e683 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5510,7 +5510,7 @@ ;; sqdmulh. -(define_insn "aarch64_sqdmulh" +(define_insn "aarch64_sqdmulh" [(set (match_operand:VSDQ_HSI 0 "register_operand" "=w") (unspec:VSDQ_HSI [(match_operand:VSDQ_HSI 1 "register_operand" "w") @@ -5521,7 +5521,7 @@ [(set_attr "type" "neon_sat_mul_")] ) -(define_insn "aarch64_sqdmulh_n" +(define_insn "aarch64_sqdmulh_n" [(set (match_operand:VDQHS 0 "register_operand" "=w") (unspec:VDQHS [(match_operand:VDQHS 1 "register_operand" "w") @@ -5535,7 +5535,7 @@ ;; sqdmulh_lane -(define_insn "aarch64_sqdmulh_lane" +(define_insn "aarch64_sqdmulh_lane" [(set (match_operand:VDQHS 0 "register_operand" "=w") (unspec:VDQHS [(match_operand:VDQHS 1 "register_operand" "w") @@ -5550,7 +5550,7 @@ [(set_attr "type" "neon_sat_mul__scalar")] ) -(define_insn "aarch64_sqdmulh_laneq" +(define_insn "aarch64_sqdmulh_laneq" [(set (match_operand:VDQHS 0 "register_operand" "=w") (unspec:VDQHS [(match_operand:VDQHS 1 "register_operand" "w") @@ -5597,7 +5597,7 @@ ;; sqrdml[as]h. -(define_insn "aarch64_sqrdmlh" +(define_insn "aarch64_sqrdmlh" [(set (match_operand:VSDQ_HSI 0 "register_operand" "=w") (unspec:VSDQ_HSI [(match_operand:VSDQ_HSI 1 "register_operand" "0") @@ -5611,7 +5611,7 @@ ;; sqrdml[as]h_lane. -(define_insn "aarch64_sqrdmlh_lane" +(define_insn "aarch64_sqrdmlh_lane" [(set (match_operand:VDQHS 0 "register_operand" "=w") (unspec:VDQHS [(match_operand:VDQHS 1 "register_operand" "0") @@ -5629,7 +5629,7 @@ [(set_attr "type" "neon_sat_mla__scalar_long")] ) -(define_insn "aarch64_sqrdmlh_lane" +(define_insn "aarch64_sqrdmlh_lane" [(set (match_operand:SD_HSI 0 "register_operand" "=w") (unspec:SD_HSI [(match_operand:SD_HSI 1 "register_operand" "0") @@ -5649,7 +5649,7 @@ ;; sqrdml[as]h_laneq. -(define_insn "aarch64_sqrdmlh_laneq" +(define_insn "aarch64_sqrdmlh_laneq" [(set (match_operand:VDQHS 0 "register_operand" "=w") (unspec:VDQHS [(match_operand:VDQHS 1 "register_operand" "0") @@ -5667,7 +5667,7 @@ [(set_attr "type" "neon_sat_mla__scalar_long")] ) -(define_insn "aarch64_sqrdmlh_laneq" +(define_insn "aarch64_sqrdmlh_laneq" [(set (match_operand:SD_HSI 0 "register_operand" "=w") (unspec:SD_HSI [(match_operand:SD_HSI 1 "register_operand" "0") diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c index 8b6548a154fb..765cb270b4ca 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c @@ -66,8 +66,8 @@ OPNINETEEN (int16, 4, 8, s16, padd, add, qadd, qsub, sub, mul, and, orr, eor, or OPNINETEEN (int32, 2, 4, s32, padd, add, qadd, qsub, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub, abd, pmax, pmin) OPSIX (int8, 8, 16, s8, zip1, zip2, uzp1, uzp2, shl, qshl) -OPSIX (int16, 4, 8, s16, zip1, zip2, uzp1, uzp2, shl, qshl) -OPSIX (int32, 2, 4, s32, zip1, zip2, uzp1, uzp2, shl, qshl) +OPEIGHT (int16, 4, 8, s16, zip1, zip2, uzp1, uzp2, shl, qshl, qdmulh, qrdmulh) +OPEIGHT (int32, 2, 4, s32, zip1, zip2, uzp1, uzp2, shl, qshl, qdmulh, qrdmulh) OPNINETEEN (uint8, 8, 16, u8, padd, add, qadd, qsub, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub, abd, pmax, pmin) OPNINETEEN (uint16, 4, 8, u16, padd, add, qadd, qsub, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub, abd, pmax, pmin) diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_10.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_10.c new file mode 100644 index 000000000000..9db54009db96 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_10.c @@ -0,0 +1,43 @@ +/* PR target/99195. */ +/* Check that we take advantage of 64-bit Advanced SIMD operations clearing + the top half of the vector register and no explicit zeroing instructions + are emitted. */ +/* { dg-do compile } */ +/* { dg-options "-O -march=armv8.1-a+rdma" } */ + +#include + +#define OPTWO(T,IS,OS,S,OP1,OP2) \ +FUNC (T, IS, OS, OP1, S) \ +FUNC (T, IS, OS, OP2, S) + +#define TERNARY(OT,IT,OP,S) \ +OT \ +foo_##OP##_##S (IT a, IT b, IT c) \ +{ \ + IT zeros = vcreate_##S (0); \ + return vcombine_##S (v##OP##_##S (a, b, c), zeros); \ +} + +#undef FUNC +#define FUNC(T,IS,OS,OP,S) TERNARY (T##x##OS##_t, T##x##IS##_t, OP, S) + +OPTWO (int16, 4, 8, s16, qrdmlah, qrdmlsh) +OPTWO (int32, 2, 4, s32, qrdmlah, qrdmlsh) + +#define TERNARY_IDX(OT,IT,OP,S) \ +OT \ +foo_##OP##_##S (IT a, IT b, IT c) \ +{ \ + IT zeros = vcreate_##S (0); \ + return vcombine_##S (v##OP##_##S (a, b, c, 0), zeros); \ +} + +#undef FUNC +#define FUNC(T,IS,OS,OP,S) TERNARY_IDX (T##x##OS##_t, T##x##IS##_t, OP, S) +OPTWO (int16, 4, 8, s16, qrdmlah_lane, qrdmlsh_lane) +OPTWO (int32, 2, 4, s32, qrdmlah_lane, qrdmlsh_lane) + +/* { dg-final { scan-assembler-not {\tfmov\t} } } */ +/* { dg-final { scan-assembler-not {\tmov\t} } } */ +