From: Florian Krohm Date: Sat, 9 Jun 2012 16:19:31 +0000 (+0000) Subject: Add a stackframe around function call. Avoids testcase hangs X-Git-Tag: svn/VALGRIND_3_8_0~240 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=54bcabbae47c27838606f0066dc6e11c4cdced53;p=thirdparty%2Fvalgrind.git Add a stackframe around function call. Avoids testcase hangs when compiled with -O3. Found and debugged by Christian. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12628 --- diff --git a/none/tests/s390x/cgij.c b/none/tests/s390x/cgij.c index d760a5d3df..962e56efb5 100644 --- a/none/tests/s390x/cgij.c +++ b/none/tests/s390x/cgij.c @@ -30,11 +30,12 @@ void compare_never(int64_t value) register int64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CGIJ(7,NEVER,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -43,11 +44,12 @@ void compare_always(int64_t value) register int64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CGIJ(7,ALWAYS,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -56,11 +58,12 @@ void compare_le42(int64_t value) register int64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CGIJ(7,LE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_gt\n\t" "j 0f\n\t" "brasl 14,if_le\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -69,11 +72,12 @@ void compare_ge42(int64_t value) register int64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CGIJ(7,GE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_lt\n\t" "j 0f\n\t" "brasl 14,if_ge\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -82,11 +86,12 @@ void compare_gt42(int64_t value) register int64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CGIJ(7,GT,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_le\n\t" "j 0f\n\t" "brasl 14,if_gt\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -95,11 +100,12 @@ void compare_lt42(int64_t value) register int64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CGIJ(7,LT,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_ge\n\t" "j 0f\n\t" "brasl 14,if_lt\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -108,11 +114,12 @@ void compare_eq42(int64_t value) register int64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CGIJ(7,EQ,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_ne\n\t" "j 0f\n\t" "brasl 14,if_eq\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -121,11 +128,12 @@ void compare_ne42(int64_t value) register int64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CGIJ(7,NE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_eq\n\t" "j 0f\n\t" "brasl 14,if_ne\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } diff --git a/none/tests/s390x/cgrj.c b/none/tests/s390x/cgrj.c index 84d4f2fcbc..f269918402 100644 --- a/none/tests/s390x/cgrj.c +++ b/none/tests/s390x/cgrj.c @@ -31,11 +31,13 @@ void compare_never(int64_t value1, int64_t value2) register int64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CGRJ(7,8,8,NEVER) "\n\t" "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -45,11 +47,13 @@ void compare_always(int64_t value1, int64_t value2) register int64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CGRJ(7,8,8,ALWAYS) "\n\t" "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -59,11 +63,13 @@ void compare_le(int64_t value1, int64_t value2) register int64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CGRJ(7,8,8,LE) "\n\t" "brasl 14,if_gt\n\t" "j 0f\n\t" "brasl 14,if_le\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -73,11 +79,13 @@ void compare_ge(int64_t value1, int64_t value2) register int64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CGRJ(7,8,8,GE) "\n\t" "brasl 14,if_lt\n\t" "j 0f\n\t" "brasl 14,if_ge\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -87,11 +95,13 @@ void compare_gt(int64_t value1, int64_t value2) register int64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CGRJ(7,8,8,GT) "\n\t" "brasl 14,if_le\n\t" "j 0f\n\t" "brasl 14,if_gt\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -101,11 +111,13 @@ void compare_lt(int64_t value1, int64_t value2) register int64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CGRJ(7,8,8,LT) "\n\t" "brasl 14,if_ge\n\t" "j 0f\n\t" "brasl 14,if_lt\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -115,11 +127,13 @@ void compare_eq(int64_t value1, int64_t value2) register int64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CGRJ(7,8,8,EQ) "\n\t" "brasl 14,if_ne\n\t" "j 0f\n\t" "brasl 14,if_eq\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -129,11 +143,13 @@ void compare_ne(int64_t value1, int64_t value2) register int64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CGRJ(7,8,8,NE) "\n\t" "brasl 14,if_eq\n\t" "j 0f\n\t" "brasl 14,if_ne\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } diff --git a/none/tests/s390x/cij.c b/none/tests/s390x/cij.c index 4e47d9896e..4f2913e89b 100644 --- a/none/tests/s390x/cij.c +++ b/none/tests/s390x/cij.c @@ -30,11 +30,12 @@ void compare_never(int32_t value) register int32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CIJ(7,NEVER,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -43,11 +44,12 @@ void compare_always(int32_t value) register int32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CIJ(7,ALWAYS,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -56,11 +58,12 @@ void compare_le42(int32_t value) register int32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CIJ(7,LE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_gt\n\t" "j 0f\n\t" "brasl 14,if_le\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -69,11 +72,12 @@ void compare_ge42(int32_t value) register int32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CIJ(7,GE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_lt\n\t" "j 0f\n\t" "brasl 14,if_ge\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -82,11 +86,12 @@ void compare_gt42(int32_t value) register int32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CIJ(7,GT,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_le\n\t" "j 0f\n\t" "brasl 14,if_gt\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -95,11 +100,12 @@ void compare_lt42(int32_t value) register int32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CIJ(7,LT,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_ge\n\t" "j 0f\n\t" "brasl 14,if_lt\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -108,11 +114,12 @@ void compare_eq42(int32_t value) register int32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CIJ(7,EQ,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_ne\n\t" "j 0f\n\t" "brasl 14,if_eq\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -121,11 +128,12 @@ void compare_ne42(int32_t value) register int32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CIJ(7,NE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_eq\n\t" "j 0f\n\t" "brasl 14,if_ne\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } diff --git a/none/tests/s390x/clgij.c b/none/tests/s390x/clgij.c index 11a8bf5620..87d3a3a367 100644 --- a/none/tests/s390x/clgij.c +++ b/none/tests/s390x/clgij.c @@ -30,11 +30,12 @@ void compare_never(uint64_t value) register uint64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLGIJ(7,NEVER,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -43,11 +44,12 @@ void compare_always(uint64_t value) register uint64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLGIJ(7,ALWAYS,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -56,11 +58,12 @@ void compare_le42(uint64_t value) register uint64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLGIJ(7,LE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_gt\n\t" "j 0f\n\t" "brasl 14,if_le\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -69,11 +72,12 @@ void compare_ge42(uint64_t value) register uint64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLGIJ(7,GE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_lt\n\t" "j 0f\n\t" "brasl 14,if_ge\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -82,11 +86,12 @@ void compare_gt42(uint64_t value) register uint64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLGIJ(7,GT,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_le\n\t" "j 0f\n\t" "brasl 14,if_gt\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -95,11 +100,12 @@ void compare_lt42(uint64_t value) register uint64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLGIJ(7,LT,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_ge\n\t" "j 0f\n\t" "brasl 14,if_lt\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -108,11 +114,12 @@ void compare_eq42(uint64_t value) register uint64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLGIJ(7,EQ,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_ne\n\t" "j 0f\n\t" "brasl 14,if_eq\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -121,11 +128,12 @@ void compare_ne42(uint64_t value) register uint64_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLGIJ(7,NE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_eq\n\t" "j 0f\n\t" "brasl 14,if_ne\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } diff --git a/none/tests/s390x/clgrj.c b/none/tests/s390x/clgrj.c index 24c7c76a24..de6b825025 100644 --- a/none/tests/s390x/clgrj.c +++ b/none/tests/s390x/clgrj.c @@ -31,11 +31,13 @@ void compare_never(uint64_t value1, uint64_t value2) register uint64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLGRJ(7,8,8,NEVER) "\n\t" "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -45,11 +47,13 @@ void compare_always(uint64_t value1, uint64_t value2) register uint64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLGRJ(7,8,8,ALWAYS) "\n\t" "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -59,11 +63,13 @@ void compare_le(uint64_t value1, uint64_t value2) register uint64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLGRJ(7,8,8,LE) "\n\t" "brasl 14,if_gt\n\t" "j 0f\n\t" "brasl 14,if_le\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -73,11 +79,13 @@ void compare_ge(uint64_t value1, uint64_t value2) register uint64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLGRJ(7,8,8,GE) "\n\t" "brasl 14,if_lt\n\t" "j 0f\n\t" "brasl 14,if_ge\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -87,11 +95,13 @@ void compare_gt(uint64_t value1, uint64_t value2) register uint64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLGRJ(7,8,8,GT) "\n\t" "brasl 14,if_le\n\t" "j 0f\n\t" "brasl 14,if_gt\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -101,11 +111,13 @@ void compare_lt(uint64_t value1, uint64_t value2) register uint64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLGRJ(7,8,8,LT) "\n\t" "brasl 14,if_ge\n\t" "j 0f\n\t" "brasl 14,if_lt\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -115,11 +127,13 @@ void compare_eq(uint64_t value1, uint64_t value2) register uint64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLGRJ(7,8,8,EQ) "\n\t" "brasl 14,if_ne\n\t" "j 0f\n\t" "brasl 14,if_eq\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -129,11 +143,13 @@ void compare_ne(uint64_t value1, uint64_t value2) register uint64_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLGRJ(7,8,8,NE) "\n\t" "brasl 14,if_eq\n\t" "j 0f\n\t" "brasl 14,if_ne\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } diff --git a/none/tests/s390x/clij.c b/none/tests/s390x/clij.c index d898d6f2d6..3b62e1c08b 100644 --- a/none/tests/s390x/clij.c +++ b/none/tests/s390x/clij.c @@ -30,11 +30,12 @@ void compare_never(uint32_t value) register uint32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLIJ(7,NEVER,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -43,11 +44,12 @@ void compare_always(uint32_t value) register uint32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLIJ(7,ALWAYS,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -56,11 +58,12 @@ void compare_le42(uint32_t value) register uint32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLIJ(7,LE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_gt\n\t" "j 0f\n\t" "brasl 14,if_le\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -69,11 +72,12 @@ void compare_ge42(uint32_t value) register uint32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLIJ(7,GE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_lt\n\t" "j 0f\n\t" "brasl 14,if_ge\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -82,11 +86,12 @@ void compare_gt42(uint32_t value) register uint32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLIJ(7,GT,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_le\n\t" "j 0f\n\t" "brasl 14,if_gt\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -95,11 +100,12 @@ void compare_lt42(uint32_t value) register uint32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLIJ(7,LT,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_ge\n\t" "j 0f\n\t" "brasl 14,if_lt\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -108,11 +114,12 @@ void compare_eq42(uint32_t value) register uint32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLIJ(7,EQ,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_ne\n\t" "j 0f\n\t" "brasl 14,if_eq\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } @@ -121,11 +128,12 @@ void compare_ne42(uint32_t value) register uint32_t val asm("r7") = value; asm volatile( + "aghi 15,-160\n\t" CLIJ(7,NE,8,2a) "\n\t" /* 0x2a == 42 */ "brasl 14,if_eq\n\t" "j 0f\n\t" "brasl 14,if_ne\n\t" - "0: nopr 0\n\t" : : "d"(val) : BRASLCLOBBER); + "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER); return; } diff --git a/none/tests/s390x/clrj.c b/none/tests/s390x/clrj.c index 3c732474fc..4e3454f4dc 100644 --- a/none/tests/s390x/clrj.c +++ b/none/tests/s390x/clrj.c @@ -31,11 +31,13 @@ void compare_never(uint32_t value1, uint32_t value2) register uint32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLRJ(7,8,8,NEVER) "\n\t" "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -45,11 +47,13 @@ void compare_always(uint32_t value1, uint32_t value2) register uint32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLRJ(7,8,8,ALWAYS) "\n\t" "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -59,11 +63,13 @@ void compare_le(uint32_t value1, uint32_t value2) register uint32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLRJ(7,8,8,LE) "\n\t" "brasl 14,if_gt\n\t" "j 0f\n\t" "brasl 14,if_le\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -73,11 +79,13 @@ void compare_ge(uint32_t value1, uint32_t value2) register uint32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLRJ(7,8,8,GE) "\n\t" "brasl 14,if_lt\n\t" "j 0f\n\t" "brasl 14,if_ge\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -87,11 +95,13 @@ void compare_gt(uint32_t value1, uint32_t value2) register uint32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLRJ(7,8,8,GT) "\n\t" "brasl 14,if_le\n\t" "j 0f\n\t" "brasl 14,if_gt\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -101,11 +111,13 @@ void compare_lt(uint32_t value1, uint32_t value2) register uint32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLRJ(7,8,8,LT) "\n\t" "brasl 14,if_ge\n\t" "j 0f\n\t" "brasl 14,if_lt\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -115,11 +127,13 @@ void compare_eq(uint32_t value1, uint32_t value2) register uint32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLRJ(7,8,8,EQ) "\n\t" "brasl 14,if_ne\n\t" "j 0f\n\t" "brasl 14,if_eq\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -129,11 +143,13 @@ void compare_ne(uint32_t value1, uint32_t value2) register uint32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CLRJ(7,8,8,NE) "\n\t" "brasl 14,if_eq\n\t" "j 0f\n\t" "brasl 14,if_ne\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } diff --git a/none/tests/s390x/crj.c b/none/tests/s390x/crj.c index 97acc85fbc..936b70cae8 100644 --- a/none/tests/s390x/crj.c +++ b/none/tests/s390x/crj.c @@ -31,11 +31,13 @@ void compare_never(int32_t value1, int32_t value2) register int32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CRJ(7,8,8,NEVER) "\n\t" "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -45,11 +47,13 @@ void compare_always(int32_t value1, int32_t value2) register int32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CRJ(7,8,8,ALWAYS) "\n\t" "brasl 14,if_not_taken\n\t" "j 0f\n\t" "brasl 14,if_taken\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -59,11 +63,13 @@ void compare_le(int32_t value1, int32_t value2) register int32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CRJ(7,8,8,LE) "\n\t" "brasl 14,if_gt\n\t" "j 0f\n\t" "brasl 14,if_le\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -73,11 +79,13 @@ void compare_ge(int32_t value1, int32_t value2) register int32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CRJ(7,8,8,GE) "\n\t" "brasl 14,if_lt\n\t" "j 0f\n\t" "brasl 14,if_ge\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -87,11 +95,13 @@ void compare_gt(int32_t value1, int32_t value2) register int32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CRJ(7,8,8,GT) "\n\t" "brasl 14,if_le\n\t" "j 0f\n\t" "brasl 14,if_gt\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -101,11 +111,13 @@ void compare_lt(int32_t value1, int32_t value2) register int32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CRJ(7,8,8,LT) "\n\t" "brasl 14,if_ge\n\t" "j 0f\n\t" "brasl 14,if_lt\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -115,11 +127,13 @@ void compare_eq(int32_t value1, int32_t value2) register int32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CRJ(7,8,8,EQ) "\n\t" "brasl 14,if_ne\n\t" "j 0f\n\t" "brasl 14,if_eq\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; } @@ -129,11 +143,13 @@ void compare_ne(int32_t value1, int32_t value2) register int32_t val2 asm("r8") = value2; asm volatile( + "aghi 15,-160\n\t" CRJ(7,8,8,NE) "\n\t" "brasl 14,if_eq\n\t" "j 0f\n\t" "brasl 14,if_ne\n\t" - "0: nopr 0\n\t" : : "d"(val1), "d"(val2) : BRASLCLOBBER); + "0: aghi 15,160\n\t" + : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); return; }