From: Julian Seward <jseward@acm.org>
Date: Fri, 24 Sep 2010 21:59:55 +0000 (+0000)
Subject: Implement RBIT in ARM mode.
X-Git-Tag: svn/VALGRIND_3_6_1^2~40
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=55067a5f3ffb864d66c7bb6a15c27773c7d470d6;p=thirdparty%2Fvalgrind.git

Implement RBIT in ARM mode.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2042
---

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index a2a02fd403..a7896471be 100644
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -13759,6 +13759,20 @@ DisResult disInstr_ARM_WRK (
       }
    }
 
+   /* ------------------- rbit ------------------ */
+   if (INSN(27,16) == 0x6FF && INSN(11,4) == 0xF3) {
+      UInt rD = INSN(15,12);
+      UInt rM = INSN(3,0);
+      if (rD != 15 && rM != 15) {
+         IRTemp arg = newTemp(Ity_I32);
+         assign(arg, getIRegA(rM));
+         IRTemp res = gen_BITREV(arg);
+         putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
+         DIP("rbit r%u, r%u\n", rD, rM);
+         goto decode_success;
+      }
+   }
+
    /* ------------------- smmul ------------------ */
    if (INSN(27,20) == BITS8(0,1,1,1,0,1,0,1)
        && INSN(15,12) == BITS4(1,1,1,1)