From: Rogerio Alves Date: Mon, 14 Jan 2019 13:53:50 +0000 (-0600) Subject: powerpc: fix tst-ucontext-ppc64-vscr test for POWER 5/6. X-Git-Tag: glibc-2.29~33 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=56054664ccf837fa325692c0359baa62c64491a1;p=thirdparty%2Fglibc.git powerpc: fix tst-ucontext-ppc64-vscr test for POWER 5/6. An error "impossible register constraint in 'asm'" was raised on POWER 5 and due to __vector __int128_t being used as operands without passing the option -msvx to gcc. This patch replaces "__vector __int128_t" with "__vector unsigned int" which requires only -maltivec, available since POWER ISA 2.03, and which is already passed to the compiler. * sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c: (do_test): Changed __vector __int128_t to __vector unsigned int. Reviewed-by: Tulio Magno Quites Machado Filho --- diff --git a/ChangeLog b/ChangeLog index 3a94b71fe72..36ce7b34e3c 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2019-01-15 Rogerio A. Cardoso + + * sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c: + (do_test): Changed __vector __int128_t to __vector unsigned int. + 2019-01-14 Leonardo Sandoval * sysdeps/x86_64/multiarch/Makefile (sysdep_routines): Add diff --git a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c index 2dcf5bb6347..dbe06c847b1 100644 --- a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c +++ b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c @@ -44,8 +44,8 @@ do_test (void) uint32_t* vscr_ptr = vscr; uint32_t vscr_word; ucontext_t ucp; - __vector __int128_t v0 = {0}; - __vector __int128_t v1 = {0}; + __vector unsigned int v0 = {0}; + __vector unsigned int v1 = {0}; /* Set SAT bit in VSCR register. */ asm volatile (".machine push;\n"