From: Richard Henderson Date: Fri, 28 May 2004 00:02:03 +0000 (-0700) Subject: backport: alpha.md (UNSPEC_NT_LDA): Renumber. X-Git-Tag: releases/gcc-3.3.4~12 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=56145bd2e8ba74ee1ac7ac4eb0313a2676320bde;p=thirdparty%2Fgcc.git backport: alpha.md (UNSPEC_NT_LDA): Renumber. Backport from mainline: 2004-01-19 Richard Henderson * alpha.md (UNSPEC_NT_LDA): Renumber. (UNSPEC_CVTLQ, cvtlq): New. (extendsidi2_1): Rename from extendsidi2_nofix; remove f/f. (extendsidi2_fix): Remove. (extendsidi2 splitter): Use cvtlq. (extendsidi2 fp peepholes): Remove. (cvtql): Use SFmode instead of SImode. (fix_trunc?fsi): Update to match. (floatsisf2_ieee, floatsisf2, floatsidf2_ieee, floatsidf2): New. (movsi): Rename from movsi_nofix, remove f alternatives. (movsi_nt_vms): Similarly. (movsi_fix, movsi_nt_vms_fix): Remove. From-SVN: r82342 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8c477a2149f2..31fcba844268 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2004-05-27 Richard Henderson + + Backport from mainline: + 2004-01-19 Richard Henderson + * alpha.md (UNSPEC_NT_LDA): Renumber. + (UNSPEC_CVTLQ, cvtlq): New. + (extendsidi2_1): Rename from extendsidi2_nofix; remove f/f. + (extendsidi2_fix): Remove. + (extendsidi2 splitter): Use cvtlq. + (extendsidi2 fp peepholes): Remove. + (cvtql): Use SFmode instead of SImode. + (fix_trunc?fsi): Update to match. + (floatsisf2_ieee, floatsisf2, floatsidf2_ieee, floatsidf2): New. + (movsi): Rename from movsi_nofix, remove f alternatives. + (movsi_nt_vms): Similarly. + (movsi_fix, movsi_nt_vms_fix): Remove. + 2004-05-26 Hans-Peter Nilsson PR optimization/15296 diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index 339403ec342c..529f7d5c844c 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -642,12 +642,11 @@ extern const char *alpha_tls_size_string; /* For -mtls-size= */ /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On Alpha, the integer registers can hold any mode. The floating-point - registers can hold 32-bit and 64-bit integers as well, but not 16-bit - or 8-bit values. */ + registers can hold 64-bit integers as well, but not smaller values. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((REGNO) >= 32 && (REGNO) <= 62 \ - ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \ + ? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \ : 1) /* Value is 1 if MODE is a supported vector mode. */ diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index f7e9fa404bc9..4352a4a47d02 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -30,7 +30,7 @@ (UNSPEC_INSXH 2) (UNSPEC_MSKXH 3) (UNSPEC_CVTQL 4) - (UNSPEC_NT_LDA 5) + (UNSPEC_CVTLQ 5) (UNSPEC_UMK_LAUM 6) (UNSPEC_UMK_LALM 7) (UNSPEC_UMK_LAL 8) @@ -58,6 +58,9 @@ (UNSPEC_PERR 26) (UNSPEC_CTLZ 27) (UNSPEC_CTPOP 28) + + ;; Legacy + (UNSPEC_NT_LDA 29) ]) ;; UNSPEC_VOLATILE: @@ -177,41 +180,36 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" "" "") -(define_insn "*extendsidi2_nofix" - [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f") - (sign_extend:DI - (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))] - "! TARGET_FIX" - "@ - addl $31,%1,%0 - ldl %0,%1 - cvtlq %1,%0 - lds %0,%1\;cvtlq %0,%0" - [(set_attr "type" "iadd,ild,fadd,fld") - (set_attr "length" "*,*,*,8")]) +(define_insn "*cvtlq" + [(set (match_operand:DI 0 "register_operand" "=f") + (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")] + UNSPEC_CVTLQ))] + "" + "cvtlq %1,%0" + [(set_attr "type" "fadd")]) -(define_insn "*extendsidi2_fix" - [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f") +(define_insn "*extendsidi2_1" + [(set (match_operand:DI 0 "register_operand" "=r,r,!*f") (sign_extend:DI - (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))] - "TARGET_FIX" + (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] + "" "@ addl $31,%1,%0 ldl %0,%1 - ftois %1,%0 - cvtlq %1,%0 lds %0,%1\;cvtlq %0,%0" - [(set_attr "type" "iadd,ild,ftoi,fadd,fld") - (set_attr "length" "*,*,*,*,8")]) + [(set_attr "type" "iadd,ild,fld") + (set_attr "length" "*,*,8")]) -;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here. (define_split [(set (match_operand:DI 0 "hard_fp_register_operand" "") (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))] "reload_completed" [(set (match_dup 2) (match_dup 1)) - (set (match_dup 0) (sign_extend:DI (match_dup 2)))] - "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));") + (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] +{ + operands[1] = adjust_address (operands[1], SFmode, 0); + operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0])); +}) ;; Optimize sign-extension of SImode loads. This shows up in the wake of ;; reload when converting fp->int. @@ -227,28 +225,6 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" (sign_extend:DI (match_dup 1)))] "") -(define_peephole2 - [(set (match_operand:SI 0 "hard_int_register_operand" "") - (match_operand:SI 1 "hard_fp_register_operand" "")) - (set (match_operand:DI 2 "hard_int_register_operand" "") - (sign_extend:DI (match_dup 0)))] - "TARGET_FIX - && (true_regnum (operands[0]) == true_regnum (operands[2]) - || peep2_reg_dead_p (2, operands[0]))" - [(set (match_dup 2) - (sign_extend:DI (match_dup 1)))] - "") - -(define_peephole2 - [(set (match_operand:DI 0 "hard_fp_register_operand" "") - (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" ""))) - (set (match_operand:DI 2 "hard_int_register_operand" "") - (match_dup 0))] - "TARGET_FIX && peep2_reg_dead_p (2, operands[0])" - [(set (match_dup 2) - (sign_extend:DI (match_dup 1)))] - "") - ;; Don't say we have addsi3 if optimizing. This generates better code. We ;; have the anonymous addsi3 pattern below in case combine wants to make it. (define_expand "addsi3" @@ -2305,8 +2281,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" ;; processing, it is cheaper to do the truncation in the int regs. (define_insn "*cvtql" - [(set (match_operand:SI 0 "register_operand" "=f") - (unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")] + [(set (match_operand:SF 0 "register_operand" "=f") + (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")] UNSPEC_CVTQL))] "TARGET_FP" "cvtql%/ %R1,%0" @@ -2318,14 +2294,16 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" [(set (match_operand:SI 0 "memory_operand" "=m") (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0)) (clobber (match_scratch:DI 2 "=&f")) - (clobber (match_scratch:SI 3 "=&f"))] + (clobber (match_scratch:SF 3 "=&f"))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "#" "&& reload_completed" [(set (match_dup 2) (fix:DI (match_dup 1))) - (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL)) - (set (match_dup 0) (match_dup 3))] - "" + (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) + (set (match_dup 5) (match_dup 3))] +{ + operands[5] = adjust_address (operands[0], SFmode, 0); +} [(set_attr "type" "fadd") (set_attr "trap" "yes")]) @@ -2337,10 +2315,12 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" "#" "&& reload_completed" [(set (match_dup 2) (fix:DI (match_dup 1))) - (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL)) - (set (match_dup 0) (match_dup 3))] - ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG. - "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));" + (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) + (set (match_dup 4) (match_dup 3))] +{ + operands[3] = gen_rtx_REG (SFmode, REGNO (operands[2])); + operands[4] = adjust_address (operands[0], SFmode, 0); +} [(set_attr "type" "fadd") (set_attr "trap" "yes")]) @@ -2371,14 +2351,16 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" (subreg:SI (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0)) (clobber (match_scratch:DI 2 "=&f")) - (clobber (match_scratch:SI 3 "=&f"))] + (clobber (match_scratch:SF 3 "=&f"))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "#" "&& reload_completed" [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1)))) - (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL)) - (set (match_dup 0) (match_dup 3))] - "" + (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) + (set (match_dup 4) (match_dup 3))] +{ + operands[4] = adjust_address (operands[0], SFmode, 0); +} [(set_attr "type" "fadd") (set_attr "trap" "yes")]) @@ -2391,10 +2373,12 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" "#" "&& reload_completed" [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1)))) - (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL)) - (set (match_dup 0) (match_dup 3))] - ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG. - "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));" + (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) + (set (match_dup 4) (match_dup 3))] +{ + operands[3] = gen_rtx_REG (SFmode, REGNO (operands[2])); + operands[4] = adjust_address (operands[0], SFmode, 0); +} [(set_attr "type" "fadd") (set_attr "trap" "yes")]) @@ -2446,6 +2430,35 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" (set_attr "round_suffix" "normal") (set_attr "trap_suffix" "sui")]) +(define_insn_and_split "*floatsisf2_ieee" + [(set (match_operand:SF 0 "register_operand" "=&f") + (float:SF (match_operand:SI 1 "memory_operand" "m"))) + (clobber (match_scratch:DI 2 "=&f")) + (clobber (match_scratch:SF 3 "=&f"))] + "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" + "#" + "&& reload_completed" + [(set (match_dup 3) (match_dup 1)) + (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) + (set (match_dup 0) (float:SF (match_dup 2)))] +{ + operands[1] = adjust_address (operands[1], SFmode, 0); +}) + +(define_insn_and_split "*floatsisf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (float:SF (match_operand:SI 1 "memory_operand" "m")))] + "TARGET_FP" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ)) + (set (match_dup 0) (float:SF (match_dup 2)))] +{ + operands[1] = adjust_address (operands[1], SFmode, 0); + operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); +}) + (define_insn "*floatdidf_ieee" [(set (match_operand:DF 0 "register_operand" "=&f") (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] @@ -2466,6 +2479,36 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" (set_attr "round_suffix" "normal") (set_attr "trap_suffix" "sui")]) +(define_insn_and_split "*floatsidf2_ieee" + [(set (match_operand:DF 0 "register_operand" "=&f") + (float:DF (match_operand:SI 1 "memory_operand" "m"))) + (clobber (match_scratch:DI 2 "=&f")) + (clobber (match_scratch:SF 3 "=&f"))] + "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" + "#" + "&& reload_completed" + [(set (match_dup 3) (match_dup 1)) + (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) + (set (match_dup 0) (float:DF (match_dup 2)))] +{ + operands[1] = adjust_address (operands[1], SFmode, 0); +}) + +(define_insn_and_split "*floatsidf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (float:DF (match_operand:SI 1 "memory_operand" "m")))] + "TARGET_FP" + "#" + "&& reload_completed" + [(set (match_dup 3) (match_dup 1)) + (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) + (set (match_dup 0) (float:DF (match_dup 2)))] +{ + operands[1] = adjust_address (operands[1], SFmode, 0); + operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); + operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0])); +}) + (define_expand "floatditf2" [(use (match_operand:TF 0 "register_operand" "")) (use (match_operand:DI 1 "general_operand" ""))] @@ -5086,27 +5129,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" operands[1] = force_reg (TFmode, operands[1]); }) -(define_insn "*movsi_nofix" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m") - (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))] - "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX - && (register_operand (operands[0], SImode) - || reg_or_0_operand (operands[1], SImode))" - "@ - bis $31,%r1,%0 - lda %0,%1($31) - ldah %0,%h1($31) - ldl %0,%1 - stl %r1,%0 - cpys %R1,%R1,%0 - ld%, %0,%1 - st%, %R1,%0" - [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")]) - -(define_insn "*movsi_fix" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f") - (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))] - "TARGET_ABI_OSF && TARGET_FIX +(define_insn "*movsi" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m") + (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ"))] + "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && (register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode))" "@ @@ -5114,38 +5140,13 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" lda %0,%1($31) ldah %0,%h1($31) ldl %0,%1 - stl %r1,%0 - cpys %R1,%R1,%0 - ld%, %0,%1 - st%, %R1,%0 - ftois %1,%0 - itofs %1,%0" - [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")]) - -(define_insn "*movsi_nt_vms_nofix" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m") - (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))] - "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS) - && !TARGET_FIX - && (register_operand (operands[0], SImode) - || reg_or_0_operand (operands[1], SImode))" - "@ - bis $31,%1,%0 - lda %0,%1 - ldah %0,%h1 - lda %0,%1 - ldl %0,%1 - stl %r1,%0 - cpys %R1,%R1,%0 - ld%, %0,%1 - st%, %R1,%0" - [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")]) + stl %r1,%0" + [(set_attr "type" "ilog,iadd,iadd,ild,ist")]) -(define_insn "*movsi_nt_vms_fix" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f") - (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))] +(define_insn "*movsi_nt_vms" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m") + (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ"))] "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS) - && TARGET_FIX && (register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode))" "@ @@ -5154,13 +5155,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" ldah %0,%h1 lda %0,%1 ldl %0,%1 - stl %r1,%0 - cpys %R1,%R1,%0 - ld%, %0,%1 - st%, %R1,%0 - ftois %1,%0 - itofs %1,%0" - [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")]) + stl %r1,%0" + [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist")]) (define_insn "*movhi_nobwx" [(set (match_operand:HI 0 "register_operand" "=r,r")