From: Ulrich Weigand Date: Wed, 18 Feb 2004 23:00:24 +0000 (+0000) Subject: s390.md ("divmodtidi3"): Use canonical RTL. X-Git-Tag: releases/gcc-4.0.0~10020 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5665e39850ca0332c4a35e0006f2c61fa28272cc;p=thirdparty%2Fgcc.git s390.md ("divmodtidi3"): Use canonical RTL. * config/s390/s390.md ("divmodtidi3"): Use canonical RTL. ("divmodtisi3"): Likewise. ("udivmoddi4", "udivmodtidi3"): Likewise. ("divmodsi4", "divmoddisi3"): Likewise. ("udivmodsi4", "udivmoddisi3"): Likewise. ("udivsi3", "umodsi3"): Likewise. From-SVN: r78057 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 795acaca21df..a2b412f460eb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2004-02-18 Ulrich Weigand + + * config/s390/s390.md ("divmodtidi3"): Use canonical RTL. + ("divmodtisi3"): Likewise. + ("udivmoddi4", "udivmodtidi3"): Likewise. + ("divmodsi4", "divmoddisi3"): Likewise. + ("udivmodsi4", "udivmoddisi3"): Likewise. + ("udivsi3", "umodsi3"): Likewise. + 2004-02-18 Ulrich Weigand * config/s390/s390.c (s390_mainpool_start): Delete the main pool diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 874b19b681f7..5cae9ba2a023 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -4575,14 +4575,12 @@ (define_insn "divmodtidi3" [(set (match_operand:TI 0 "register_operand" "=d,d") (ior:TI - (zero_extend:TI - (div:DI (match_operand:DI 1 "register_operand" "0,0") - (match_operand:DI 2 "general_operand" "d,m"))) (ashift:TI (zero_extend:TI - (mod:DI (match_dup 1) - (match_dup 2))) - (const_int 64))))] + (mod:DI (match_operand:DI 1 "register_operand" "0,0") + (match_operand:DI 2 "general_operand" "d,m"))) + (const_int 64)) + (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] "TARGET_64BIT" "@ dsgr\t%0,%2 @@ -4593,14 +4591,14 @@ (define_insn "divmodtisi3" [(set (match_operand:TI 0 "register_operand" "=d,d") (ior:TI - (zero_extend:TI - (div:DI (match_operand:DI 1 "register_operand" "0,0") - (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) (ashift:TI (zero_extend:TI - (mod:DI (match_dup 1) - (sign_extend:DI (match_dup 2)))) - (const_int 64))))] + (mod:DI (match_operand:DI 1 "register_operand" "0,0") + (sign_extend:DI + (match_operand:SI 2 "nonimmediate_operand" "d,m")))) + (const_int 64)) + (zero_extend:TI + (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] "TARGET_64BIT" "@ dsgfr\t%0,%2 @@ -4626,10 +4624,10 @@ div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); equal = gen_rtx_IOR (TImode, - gen_rtx_ZERO_EXTEND (TImode, div_equal), gen_rtx_ASHIFT (TImode, gen_rtx_ZERO_EXTEND (TImode, mod_equal), - GEN_INT (64))); + GEN_INT (64)), + gen_rtx_ZERO_EXTEND (TImode, div_equal)); operands[4] = gen_reg_rtx(TImode); emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); @@ -4652,16 +4650,17 @@ (define_insn "udivmodtidi3" [(set (match_operand:TI 0 "register_operand" "=d,d") - (ior:TI (zero_extend:TI - (truncate:DI - (udiv:TI (match_operand:TI 1 "register_operand" "0,0") - (zero_extend:TI - (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) - (ashift:TI - (zero_extend:TI - (truncate:DI - (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2))))) - (const_int 64))))] + (ior:TI + (ashift:TI + (zero_extend:TI + (truncate:DI + (umod:TI (match_operand:TI 1 "register_operand" "0,0") + (zero_extend:TI + (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) + (const_int 64)) + (zero_extend:TI + (truncate:DI + (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] "TARGET_64BIT" "@ dlgr\t%0,%2 @@ -4687,10 +4686,10 @@ div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); equal = gen_rtx_IOR (DImode, - gen_rtx_ZERO_EXTEND (DImode, div_equal), gen_rtx_ASHIFT (DImode, gen_rtx_ZERO_EXTEND (DImode, mod_equal), - GEN_INT (32))); + GEN_INT (32)), + gen_rtx_ZERO_EXTEND (DImode, div_equal)); operands[4] = gen_reg_rtx(DImode); emit_insn (gen_extendsidi2 (operands[4], operands[1])); @@ -4711,16 +4710,17 @@ (define_insn "divmoddisi3" [(set (match_operand:DI 0 "register_operand" "=d,d") - (ior:DI (zero_extend:DI - (truncate:SI - (div:DI (match_operand:DI 1 "register_operand" "0,0") - (sign_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) - (ashift:DI - (zero_extend:DI - (truncate:SI - (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2))))) - (const_int 32))))] + (ior:DI + (ashift:DI + (zero_extend:DI + (truncate:SI + (mod:DI (match_operand:DI 1 "register_operand" "0,0") + (sign_extend:DI + (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) + (const_int 32)) + (zero_extend:DI + (truncate:SI + (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] "!TARGET_64BIT" "@ dr\t%0,%2 @@ -4746,10 +4746,10 @@ div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); equal = gen_rtx_IOR (DImode, - gen_rtx_ZERO_EXTEND (DImode, div_equal), gen_rtx_ASHIFT (DImode, gen_rtx_ZERO_EXTEND (DImode, mod_equal), - GEN_INT (32))); + GEN_INT (32)), + gen_rtx_ZERO_EXTEND (DImode, div_equal)); operands[4] = gen_reg_rtx(DImode); emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); @@ -4772,16 +4772,17 @@ (define_insn "udivmoddisi3" [(set (match_operand:DI 0 "register_operand" "=d,d") - (ior:DI (zero_extend:DI - (truncate:SI - (udiv:DI (match_operand:DI 1 "register_operand" "0,0") - (zero_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) - (ashift:DI - (zero_extend:DI - (truncate:SI - (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2))))) - (const_int 32))))] + (ior:DI + (ashift:DI + (zero_extend:DI + (truncate:SI + (umod:DI (match_operand:DI 1 "register_operand" "0,0") + (zero_extend:DI + (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) + (const_int 32)) + (zero_extend:DI + (truncate:SI + (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] "!TARGET_64BIT && TARGET_CPU_ZARCH" "@ dlr\t%0,%2 @@ -4801,10 +4802,10 @@ udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); equal = gen_rtx_IOR (DImode, - gen_rtx_ZERO_EXTEND (DImode, udiv_equal), gen_rtx_ASHIFT (DImode, gen_rtx_ZERO_EXTEND (DImode, umod_equal), - GEN_INT (32))); + GEN_INT (32)), + gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); operands[3] = gen_reg_rtx (DImode); @@ -4892,10 +4893,10 @@ udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); equal = gen_rtx_IOR (DImode, - gen_rtx_ZERO_EXTEND (DImode, udiv_equal), gen_rtx_ASHIFT (DImode, gen_rtx_ZERO_EXTEND (DImode, umod_equal), - GEN_INT (32))); + GEN_INT (32)), + gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); operands[3] = gen_reg_rtx (DImode);