From: Maciej W. Rozycki Date: Wed, 22 Nov 2023 01:18:27 +0000 (+0000) Subject: RISC-V: Also accept constants for T-Head cond-move data input operands X-Git-Tag: basepoints/gcc-15~4419 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=566a2b3baa342c7e00b7de7112d92637baba9c75;p=thirdparty%2Fgcc.git RISC-V: Also accept constants for T-Head cond-move data input operands There is no need for the requirement for conditional-move data input operands to be stricter for T-Head targets than for short forward branch targets and limit them to registers only. They are keyed according to the `sfb_alu_operand' predicate, which lets certain constants through. Such constants are already forced into a register for the `cons' operand in the analogous short forward branch case and we can force them for the `alt' operand and T-Head as well. This enables more opportunities for a branchless sequence to be produced. gcc/ * config/riscv/riscv.cc (riscv_expand_conditional_move): Also accept constants for T-Head data input operands. --- diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ac2e76f4bedf..cdd1a4f9e254 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4123,8 +4123,6 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) if (TARGET_XTHEADCONDMOV && GET_MODE_CLASS (mode) == MODE_INT - && reg_or_0_operand (cons, mode) - && reg_or_0_operand (alt, mode) && (GET_MODE (op) == mode || GET_MODE (op) == E_VOIDmode) && (GET_MODE (op0) == mode || CONST_INT_P (op0)) && (GET_MODE (op1) == mode || CONST_INT_P (op1)) @@ -4142,6 +4140,8 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) cases for extensions which are more general than SFB. But does mean we need to force CONS into a register at this point. */ cons = force_reg (mode, cons); + /* With XTheadCondMov we need to force ALT into a register too. */ + alt = force_reg (mode, alt); emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, cons, alt))); return true;