From: Drew Fustini <dfustini@oss.tenstorrent.com>
Date: Tue, 14 Oct 2025 03:11:55 +0000 (-0700)
Subject: dt-bindings: riscv: cpus: Add SiFive X280 compatible
X-Git-Tag: v6.19-rc1~99^2~2^2~5
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=571e42a1197c432d6bb78e1feb9586b4feb0a981;p=thirdparty%2Fkernel%2Fstable.git

dt-bindings: riscv: cpus: Add SiFive X280 compatible

Document compatible for the SiFive X280 RISC-V core.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Joel Stanley <jms@oss.tenstorrent.com>
Signed-off-by: Drew Fustini <dfustini@oss.tenstorrent.com>
---

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 153d0dac57fb3..afb8533f6a081 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -70,6 +70,7 @@ properties:
           - enum:
               - sifive,e51
               - sifive,u54-mc
+              - sifive,x280
           - const: sifive,rocket0
           - const: riscv
       - const: riscv    # Simulator only