From: Michael Brown Date: Tue, 30 Apr 2013 12:36:04 +0000 (+0100) Subject: [realtek] Allow reaction time between writing RTL_CAPR and reading RTL_CR X-Git-Tag: v1.20.1~1520 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=592755eccf51c87ca727c2044eee7ffc3266e290;p=thirdparty%2Fipxe.git [realtek] Allow reaction time between writing RTL_CAPR and reading RTL_CR Some older RTL8139 chips seem to not immediately update the RTL_CR.BUFE bit in response to a write to RTL_CAPR. This results in iPXE seeing a spurious zero-length received packet, and thereafter being out of sync with the hardware's RX ring offset. Fix by inserting an extra PCI read cycle after writing to RTL_CAPR, to give the chip time to react before we next read RTL_CR. Reported-by: Gelip Tested-by: Gelip Signed-off-by: Michael Brown --- diff --git a/src/drivers/net/realtek.c b/src/drivers/net/realtek.c index d7c4d29d4..70c0ac1c6 100644 --- a/src/drivers/net/realtek.c +++ b/src/drivers/net/realtek.c @@ -861,6 +861,9 @@ static void realtek_legacy_poll_rx ( struct net_device *netdev ) { rtl->rx_offset = ( ( rtl->rx_offset + 3 ) & ~3 ); rtl->rx_offset = ( rtl->rx_offset % RTL_RXBUF_LEN ); writew ( ( rtl->rx_offset - 16 ), rtl->regs + RTL_CAPR ); + + /* Give chip time to react before rechecking RTL_CR */ + readw ( rtl->regs + RTL_CAPR ); } }