From: Pan Li Date: Thu, 21 Nov 2024 06:30:48 +0000 (+0800) Subject: RISC-V: Refactor the test files for all other vector SAT ALU X-Git-Tag: basepoints/gcc-16~3927 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=59afd30c48d935188dd795c805f0b03121068bfe;p=thirdparty%2Fgcc.git RISC-V: Refactor the test files for all other vector SAT ALU This patch would like to refactor the all the other testcases of vector SAT ALU after move to rvv/autovec/sat folder. Includes: * Refine the include header files. * Remove unnecessary optimization options. * Reconcile the dump check based on option no-opts and/or any-opts. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c: Refine the include file, remove unnecessary options and reconcile the dump check based on options. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c: Ditto. * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Removed. Signed-off-by: Pan Li --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c index 12d8c01d67f4..38d105752377 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c index 338e4150f024..b1d0ad03dae3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c index 83ccd4bb8685..a7cb22d2fb4a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c index 06b41046328e..28c24296dab9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c index dec0359c5ed9..19c76774a9ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c index 72b2d6778cca..572a4bd11277 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c index 3ca44589e427..f41e939cd370 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c index e3a7bfcf161c..af21bf3b8576 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c index c10dc0903c45..88304e985fab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c index d1352ed56e4c..f5a312e67f4a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c index b86887d332bf..327572152828 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c index 79ce8dc5d3ec..8b3953f18613 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c index 4497f0c1f83c..7057c6a275e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c index 9f06e6a76509..f9c968d6b27c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c index e806fd06c003..cd96056d43c0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c index 254bb18ee3c1..24dfbe946394 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c index 7dc8e10ef468..f21061f0a72a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c index b304cd6ea281..635341e0e059 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c index 228c5a88c592..bfdf829ca384 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c index af408372ba6a..6ea5ae8eb2ec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c index 89cd45036d1a..2286e6ae4310 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c index aa91300111a6..051bf7e5de21 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c index 061070302323..12879ba9588a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c index 3b2a24d321e4..9c5b0a4da2c1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c index 9e26214dab56..95fac36740b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c index ed6bc57b59be..a35ffb87c81c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c index d62a4a786acd..d112f272f07e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c index 56b0f22825be..ee3c12cbcd33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c index 974fd4054ffe..e12d7d711462 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c index 375a59bb6a9a..dd17f1857e04 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c index 2a301ece90d3..065245ca597a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c index 51dd327994df..a0093072ff1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c index dd87dfd0f64e..51a3b1d065e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int16_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c index caf646f9520d..95a11e96a66d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int32_t, INT16_MIN, INT16_MAX) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c index f06267a5c474..1f40a2e8fc7b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int32_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c index f784937fd482..4a5bdfc1fd4a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int64_t, INT16_MIN, INT16_MAX) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c index 1e5289c751c9..034bff3b34f3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c index 2fb604b7ddcd..f437c54508c0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int64_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c index 3e26e788c083..1a0e2d58dbac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int16_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c index 63797705a04a..88bc1f77cc54 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int32_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c index aa996f3e4162..d56dd050ab26 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int32_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c index 2a15556632dc..db23955415f3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int64_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c index d9649fc86566..f9c30fadb48f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_2(int32_t, int64_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c index 1ad2b3f2546a..a1b21ab805ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int64_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c index 392366def060..933043717608 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int16_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c index 2b16049994a5..c17b25fd68b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int32_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c index b444d2ea9c64..1adc420078cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int32_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c index 06606581e8fd..b215b4dbd631 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int64_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c index 72ec727274b2..13e68df011ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_3(int32_t, int64_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c index 7915d5417a51..7bd230393e58 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int64_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c index 2ac96aa1a35b..9b85ac5250fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int16_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c index 7fe8f2774767..912e2b73526a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int32_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c index 96500562cc3c..f831f79b05f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int32_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c index b1ed04f0e4e0..f67afcd4e098 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int64_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c index 94afc448d07a..d0bf273df336 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_4(int32_t, int64_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c index 483c9e833a74..d7ea8582184a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int64_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c index 49c076ad2779..c62175ecbf75 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int16_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c index a2a1aa40e017..0e5fe79d9630 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int32_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c index ba09734efb91..90f1a3a2f6ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int32_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c index 7bc191d03567..69f397a90a7d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int64_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c index b896cbea5a68..53a8f86f0f30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_5(int32_t, int64_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c index 67477e5351ca..af49f56d1929 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int64_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c index c97057355c40..f2790d8ead08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int16_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c index 629c07347bb9..c68eaf7b45ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int32_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c index c70c8321c068..7f81ee119cf8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int32_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c index d1967baf901d..f7da85278245 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int64_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c index 8e2625fbed16..b3d3d07cc142 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_6(int32_t, int64_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c index b75a82e342cf..c16337cdc682 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int64_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c index a6eb2d5b0b2f..171efe722a32 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int16_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c index fd01c74d2df9..9d0e1fdd82d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int32_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c index 6af61538d59b..8175a70239c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int32_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c index aee896e3df3e..2f6a1ea60ee3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int64_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c index ce3ca80e416d..3862e85b513a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_7(int32_t, int64_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c index b3cb744dd97e..dcde698db485 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int64_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c index 64f140f764e6..4fc64a281c48 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int16_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c index 9bd95a52a012..c80621a10479 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int32_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c index 0cb9d7796ef4..a60ff87c8a7a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int32_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c index 8d766e33e88f..1257dc6427e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int64_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c index 98ede144020c..9a1fe30bc51b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_8(int32_t, int64_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c index 2d9870f6c2b1..7d6a8e26703d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c @@ -1,9 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int64_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts + "-O3" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts + "-O2" + } } } } */ /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c index 508cf348fc9e..c04a4ce01672 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c index 3b7c3b6a8821..a4eb523868c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c index 508cf348fc9e..c04a4ce01672 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c index 4a049ce679a2..814ca8972e25 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c index 15b6670b1c85..8540ca053470 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c index 5a1dd857b440..d15ba0ada716 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c index a98447de11f7..0be8714d96a3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c index 93f40b674fd8..2691d118ecdb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c index a98447de11f7..0be8714d96a3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c index c946ac322644..b9d0483eaa9f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c index 1d3b03471f9c..97fd9aef2b99 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c index 98a637e91e70..1798ef6fbae2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c index 0b658f3d0aa8..bf84ce0b2240 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c index 41e1789dd62a..cbaeb83fe684 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c index 0b658f3d0aa8..bf84ce0b2240 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c index 28cd5c806f93..7004c369a817 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c index a6501f93df70..43cff846d71e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c index eef36e8dbdb6..e1455615b72a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c index d07b736f5e73..e3f3584010d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c index 06afa3fff686..5e36e39d4687 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c index d07b736f5e73..e3f3584010d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c index de26b5cec1bf..cbfac223a219 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c index c1907f7d87a1..e5fad5287d78 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c index 645d7648ab59..480ff99ed4e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c index c2b7b7b12898..b924cc82ced8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c index 238e0d76c34e..1751bcb15783 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c index c2b7b7b12898..b924cc82ced8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c index e5ef086c65a2..3d9ddd6a2922 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c index 61158efdcc9b..84dc72825916 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c index b688c1190fc5..1a0133dd608c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c index 457abd6ee078..7c7f404c9e0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c index 694a771689c3..34a07b98e151 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c index 457abd6ee078..7c7f404c9e0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c index 6fb64a3e5ffd..bb8058dd411a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c index 0c8bc7458ae3..a9929c733dda 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c index 3c4513cad758..87634e51496c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c index 53c046436eaf..2f1e111649a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c index 132de83458d9..55ca0cdebcfe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c index 53c046436eaf..2f1e111649a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c index 3747149cdb78..09e08abf65bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c index 8a85d40dc083..98dc64d36013 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c index 11f758ffda36..2a157468025e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c index 4964599d5456..e36aeedef11f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c index 6c424b2bfa0c..158f00eee794 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c index 4964599d5456..e36aeedef11f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c index e7b6cdb9c947..57d9b47f041c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c index 02456e900f9d..730ef4e21b64 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c index 23cc7f0248ec..56fa74bf84ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 int8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c index 63d2391a63ea..972629adac94 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-std=c99" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" #include "vec_sat_data.h" #define T1 uint16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c index 16ff0c63e5a7..51f1ee505f61 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c @@ -1,10 +1,20 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */ -#include "../vec_sat_arith.h" +#include "vec_sat_arith.h" DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ -/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 6 "expand" { target { any-opts + "-mrvv-vector-bits=scalable" + } } } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts + "-mrvv-vector-bits=zvl" + } } } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 3 { target { any-ops + "-mrvv-vector-bits=scalable" + } } } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 2 { target { any-ops + "-mrvv-vector-bits=zvl" + } } } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h deleted file mode 100644 index cb419553926d..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ /dev/null @@ -1,886 +0,0 @@ -#ifndef HAVE_VEC_SAT_ARITH -#define HAVE_VEC_SAT_ARITH - -#include -#include - -#define VALIDATE_RESULT(out, expect, N) \ - do \ - { \ - for (unsigned i = 0; i < N; i++) \ - if (out[i] != expect[i]) __builtin_abort (); \ - } \ - while (false) - -/******************************************************************************/ -/* Saturation Add (unsigned and signed) */ -/******************************************************************************/ -#define DEF_VEC_SAT_U_ADD_FMT_1(T) \ -void __attribute__((noinline)) \ -vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = (x + y) | (-(T)((T)(x + y) < x)); \ - } \ -} - -#define DEF_VEC_SAT_U_ADD_FMT_2(T) \ -void __attribute__((noinline)) \ -vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = (T)(x + y) >= x ? (x + y) : -1; \ - } \ -} - -#define DEF_VEC_SAT_U_ADD_FMT_3(T) \ -void __attribute__((noinline)) \ -vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T ret; \ - T overflow = __builtin_add_overflow (x, y, &ret); \ - out[i] = (T)(-overflow) | ret; \ - } \ -} - -#define DEF_VEC_SAT_U_ADD_FMT_4(T) \ -void __attribute__((noinline)) \ -vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T ret; \ - out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret; \ - } \ -} - -#define DEF_VEC_SAT_U_ADD_FMT_5(T) \ -void __attribute__((noinline)) \ -vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T ret; \ - out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \ - } \ -} - -#define DEF_VEC_SAT_U_ADD_FMT_6(T) \ -void __attribute__((noinline)) \ -vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = x <= (T)(x + y) ? (x + y) : -1; \ - } \ -} - -#define DEF_VEC_SAT_U_ADD_FMT_7(T) \ -void __attribute__((noinline)) \ -vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = (T)(x + y) < x ? -1 : (x + y); \ - } \ -} - -#define DEF_VEC_SAT_U_ADD_FMT_8(T) \ -void __attribute__((noinline)) \ -vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = x > (T)(x + y) ? -1 : (x + y); \ - } \ -} - -#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \ - vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_ADD_FMT_2(T, out, op_1, op_2, N) \ - vec_sat_u_add_##T##_fmt_2(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_ADD_FMT_3(T, out, op_1, op_2, N) \ - vec_sat_u_add_##T##_fmt_3(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_ADD_FMT_4(T, out, op_1, op_2, N) \ - vec_sat_u_add_##T##_fmt_4(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_ADD_FMT_5(T, out, op_1, op_2, N) \ - vec_sat_u_add_##T##_fmt_5(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_ADD_FMT_6(T, out, op_1, op_2, N) \ - vec_sat_u_add_##T##_fmt_6(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_ADD_FMT_7(T, out, op_1, op_2, N) \ - vec_sat_u_add_##T##_fmt_7(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \ - vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N) - -#define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) \ -T __attribute__((noinline)) \ -vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1; \ -} -#define DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, IMM) \ - DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) - -#define DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM) \ -T __attribute__((noinline)) \ -vec_sat_u_add_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - out[i] = (T)(in[i] + IMM) < in[i] ? -1 : (in[i] + IMM); \ -} -#define DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, IMM) \ - DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM) - -#define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) \ -T __attribute__((noinline)) \ -vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \ -{ \ - unsigned i; \ - T ret; \ - for (i = 0; i < limit; i++) \ - { \ - out[i] = __builtin_add_overflow (in[i], IMM, &ret) ? -1 : ret; \ - } \ -} -#define DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, IMM) \ - DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) - -#define DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM) \ -T __attribute__((noinline)) \ -vec_sat_u_add_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit) \ -{ \ - unsigned i; \ - T ret; \ - for (i = 0; i < limit; i++) \ - { \ - out[i] = __builtin_add_overflow (in[i], IMM, &ret) == 0 ? ret : -1; \ - } \ -} -#define DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, IMM) \ - DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM) - -#define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \ - vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N); \ - VALIDATE_RESULT (out, expect, N) -#define RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \ - RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) - -#define RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N) \ - vec_sat_u_add_imm##IMM##_##T##_fmt_2(out, op_1, N); \ - VALIDATE_RESULT (out, expect, N) -#define RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, out, op_1, expect, IMM, N) \ - RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N) - -#define RUN_VEC_SAT_U_ADD_IMM_FMT_3(T, out, op_1, expect, IMM, N) \ - vec_sat_u_add_imm##IMM##_##T##_fmt_3(out, op_1, N); \ - VALIDATE_RESULT (out, expect, N) -#define RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, out, op_1, expect, IMM, N) \ - RUN_VEC_SAT_U_ADD_IMM_FMT_3(T, out, op_1, expect, IMM, N) - -#define RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N) \ - vec_sat_u_add_imm##IMM##_##T##_fmt_4(out, op_1, N); \ - VALIDATE_RESULT (out, expect, N) -#define RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, out, op_1, expect, IMM, N) \ - RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N) - -#define DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T sum = (UT)x + (UT)y; \ - out[i] = (x ^ y) < 0 \ - ? sum \ - : (sum ^ x) >= 0 \ - ? sum \ - : x < 0 ? MIN : MAX; \ - } \ -} -#define DEF_VEC_SAT_S_ADD_FMT_1_WRAP(T, UT, MIN, MAX) \ - DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) - -#define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T sum = (UT)x + (UT)y; \ - if ((x ^ y) < 0 || (sum ^ x) >= 0) \ - out[i] = sum; \ - else \ - out[i] = x < 0 ? MIN : MAX; \ - } \ -} -#define DEF_VEC_SAT_S_ADD_FMT_2_WRAP(T, UT, MIN, MAX) \ - DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX) - -#define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T sum; \ - bool overflow = __builtin_add_overflow (x, y, &sum); \ - out[i] = overflow ? x < 0 ? MIN : MAX : sum; \ - } \ -} -#define DEF_VEC_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \ - DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) - -#define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T sum; \ - bool overflow = __builtin_add_overflow (x, y, &sum); \ - out[i] = !overflow ? sum : x < 0 ? MIN : MAX; \ - } \ -} -#define DEF_VEC_SAT_S_ADD_FMT_4_WRAP(T, UT, MIN, MAX) \ - DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX) - -#define RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N) \ - vec_sat_s_add_##T##_fmt_1(out, op_1, op_2, N) -#define RUN_VEC_SAT_S_ADD_FMT_1_WRAP(T, out, op_1, op_2, N) \ - RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N) - -#define RUN_VEC_SAT_S_ADD_FMT_2(T, out, op_1, op_2, N) \ - vec_sat_s_add_##T##_fmt_2(out, op_1, op_2, N) -#define RUN_VEC_SAT_S_ADD_FMT_2_WRAP(T, out, op_1, op_2, N) \ - RUN_VEC_SAT_S_ADD_FMT_2(T, out, op_1, op_2, N) - -#define RUN_VEC_SAT_S_ADD_FMT_3(T, out, op_1, op_2, N) \ - vec_sat_s_add_##T##_fmt_3(out, op_1, op_2, N) -#define RUN_VEC_SAT_S_ADD_FMT_3_WRAP(T, out, op_1, op_2, N) \ - RUN_VEC_SAT_S_ADD_FMT_3(T, out, op_1, op_2, N) - -#define RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N) \ - vec_sat_s_add_##T##_fmt_4(out, op_1, op_2, N) -#define RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N) \ - RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N) - -/******************************************************************************/ -/* Saturation Sub (Unsigned and Signed) */ -/******************************************************************************/ -#define DEF_VEC_SAT_U_SUB_FMT_1(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = (x - y) & (-(T)(x >= y)); \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_FMT_2(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = (x - y) & (-(T)(x > y)); \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_FMT_3(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = x > y ? x - y : 0; \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_FMT_4(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = x >= y ? x - y : 0; \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_FMT_5(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = x < y ? 0 : x - y; \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_FMT_6(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - out[i] = x <= y ? 0 : x - y; \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_FMT_7(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T ret; \ - T overflow = __builtin_sub_overflow (x, y, &ret); \ - out[i] = ret & (T)(overflow - 1); \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_FMT_8(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T ret; \ - T overflow = __builtin_sub_overflow (x, y, &ret); \ - out[i] = ret & (T)-(!overflow); \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_FMT_9(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T ret; \ - bool overflow = __builtin_sub_overflow (x, y, &ret); \ - out[i] = overflow ? 0 : ret; \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_FMT_10(T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T ret; \ - bool overflow = __builtin_sub_overflow (x, y, &ret); \ - out[i] = !overflow ? ret : 0; \ - } \ -} - -#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \ -{ \ - T2 a; \ - T1 *p = x; \ - do { \ - a = *--p; \ - *p = (T1)(a >= b ? a - b : 0); \ - } while (--limit); \ -} -#define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2) - -#define DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0; \ -} - -#define DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, IMM) \ - DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM) - -#define RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N) \ - vec_sat_u_sub_imm##IMM##_##T##_fmt_1(out, op_1, N); \ - VALIDATE_RESULT (out, expect, N) -#define RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \ - RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N) - -#define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T minus = (UT)x - (UT)y; \ - out[i] = (x ^ y) >= 0 \ - ? minus \ - : (minus ^ x) >= 0 \ - ? minus \ - : x < 0 ? MIN : MAX; \ - } \ -} -#define DEF_VEC_SAT_S_SUB_FMT_1_WRAP(T, UT, MIN, MAX) \ - DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) - -#define DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T minus = (UT)x - (UT)y; \ - out[i] = (x ^ y) >= 0 || (minus ^ x) >= 0 \ - ? minus : x < 0 ? MIN : MAX; \ - } \ -} -#define DEF_VEC_SAT_S_SUB_FMT_2_WRAP(T, UT, MIN, MAX) \ - DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX) - -#define DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T minus; \ - bool overflow = __builtin_sub_overflow (x, y, &minus); \ - out[i] = overflow ? x < 0 ? MIN : MAX : minus; \ - } \ -} -#define DEF_VEC_SAT_S_SUB_FMT_3_WRAP(T, UT, MIN, MAX) \ - DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX) - -#define DEF_VEC_SAT_S_SUB_FMT_4(T, UT, MIN, MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - T x = op_1[i]; \ - T y = op_2[i]; \ - T minus; \ - bool overflow = __builtin_sub_overflow (x, y, &minus); \ - out[i] = !overflow ? minus : x < 0 ? MIN : MAX; \ - } \ -} -#define DEF_VEC_SAT_S_SUB_FMT_4_WRAP(T, UT, MIN, MAX) \ - DEF_VEC_SAT_S_SUB_FMT_4(T, UT, MIN, MAX) - -#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_2(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_2(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_3(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_7(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_8(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_9(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \ - vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N) - -#define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ - vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N) -#define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \ - RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ - -#define RUN_VEC_SAT_S_SUB_FMT_1(T, out, op_1, op_2, N) \ - vec_sat_s_sub_##T##_fmt_1(out, op_1, op_2, N) -#define RUN_VEC_SAT_S_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) \ - RUN_VEC_SAT_S_SUB_FMT_1(T, out, op_1, op_2, N) - -#define RUN_VEC_SAT_S_SUB_FMT_2(T, out, op_1, op_2, N) \ - vec_sat_s_sub_##T##_fmt_2(out, op_1, op_2, N) -#define RUN_VEC_SAT_S_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) \ - RUN_VEC_SAT_S_SUB_FMT_2(T, out, op_1, op_2, N) - -#define RUN_VEC_SAT_S_SUB_FMT_3(T, out, op_1, op_2, N) \ - vec_sat_s_sub_##T##_fmt_3(out, op_1, op_2, N) -#define RUN_VEC_SAT_S_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) \ - RUN_VEC_SAT_S_SUB_FMT_3(T, out, op_1, op_2, N) - -#define RUN_VEC_SAT_S_SUB_FMT_4(T, out, op_1, op_2, N) \ - vec_sat_s_sub_##T##_fmt_4(out, op_1, op_2, N) -#define RUN_VEC_SAT_S_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) \ - RUN_VEC_SAT_S_SUB_FMT_4(T, out, op_1, op_2, N) - -/******************************************************************************/ -/* Saturation Sub Truncated (Unsigned and Signed) */ -/******************************************************************************/ -#define DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T) \ -void __attribute__((noinline)) \ -vec_sat_u_sub_trunc_##OUT_T##_fmt_1 (OUT_T *out, IN_T *op_1, IN_T y, \ - unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - IN_T x = op_1[i]; \ - out[i] = (OUT_T)(x >= y ? x - y : 0); \ - } \ -} - -#define RUN_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T, out, op_1, y, N) \ - vec_sat_u_sub_trunc_##OUT_T##_fmt_1(out, op_1, y, N) - -/******************************************************************************/ -/* Saturation Truncation (Unsigned and Signed) */ -/******************************************************************************/ -#define DEF_VEC_SAT_U_TRUNC_FMT_1(NT, WT) \ -void __attribute__((noinline)) \ -vec_sat_u_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT x = in[i]; \ - bool overflow = x > (WT)(NT)(-1); \ - out[i] = ((NT)x) | (NT)-overflow; \ - } \ -} -#define DEF_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_1(NT, WT) - -#define DEF_VEC_SAT_U_TRUNC_FMT_2(NT, WT) \ -void __attribute__((noinline)) \ -vec_sat_u_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT max = (WT)(NT)-1; \ - out[i] = in[i] > max ? (NT)max : (NT)in[i]; \ - } \ -} -#define DEF_VEC_SAT_U_TRUNC_FMT_2_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_2(NT, WT) - -#define DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT) \ -void __attribute__((noinline)) \ -vec_sat_u_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT max = (WT)(NT)-1; \ - out[i] = in[i] <= max ? (NT)in[i] : (NT)max; \ - } \ -} -#define DEF_VEC_SAT_U_TRUNC_FMT_3_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT) - -#define DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT) \ -void __attribute__((noinline)) \ -vec_sat_u_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - bool not_overflow = in[i] <= (WT)(NT)(-1); \ - out[i] = ((NT)in[i]) | (NT)((NT)not_overflow - 1); \ - } \ -} -#define DEF_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT) - -#define DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT x = in[i]; \ - NT trunc = (NT)x; \ - out[i] = (WT)NT_MIN <= x && x <= (WT)NT_MAX \ - ? trunc \ - : x < 0 ? NT_MIN : NT_MAX; \ - } \ -} -#define DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, NT_MIN, NT_MAX) \ - DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX) - -#define DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT x = in[i]; \ - NT trunc = (NT)x; \ - out[i] = (WT)NT_MIN < x && x < (WT)NT_MAX \ - ? trunc \ - : x < 0 ? NT_MIN : NT_MAX; \ - } \ -} -#define DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, NT_MIN, NT_MAX) \ - DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX) - -#define DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT x = in[i]; \ - NT trunc = (NT)x; \ - out[i] = (WT)NT_MIN < x && x <= (WT)NT_MAX \ - ? trunc \ - : x < 0 ? NT_MIN : NT_MAX; \ - } \ -} -#define DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, NT_MIN, NT_MAX) \ - DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX) - -#define DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT x = in[i]; \ - NT trunc = (NT)x; \ - out[i] = (WT)NT_MIN <= x && x < (WT)NT_MAX \ - ? trunc \ - : x < 0 ? NT_MIN : NT_MAX; \ - } \ -} -#define DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, NT_MIN, NT_MAX) \ - DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX) - -#define DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_trunc_##NT##_##WT##_fmt_5 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT x = in[i]; \ - NT trunc = (NT)x; \ - out[i] = (WT)NT_MIN > x || x > (WT)NT_MAX \ - ? x < 0 ? NT_MIN : NT_MAX \ - : trunc; \ - } \ -} -#define DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, NT_MIN, NT_MAX) \ - DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX) - -#define DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_trunc_##NT##_##WT##_fmt_6 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT x = in[i]; \ - NT trunc = (NT)x; \ - out[i] = (WT)NT_MIN >= x || x > (WT)NT_MAX \ - ? x < 0 ? NT_MIN : NT_MAX \ - : trunc; \ - } \ -} -#define DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, NT_MIN, NT_MAX) \ - DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX) - -#define DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_trunc_##NT##_##WT##_fmt_7 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT x = in[i]; \ - NT trunc = (NT)x; \ - out[i] = (WT)NT_MIN > x || x >= (WT)NT_MAX \ - ? x < 0 ? NT_MIN : NT_MAX \ - : trunc; \ - } \ -} -#define DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, NT_MIN, NT_MAX) \ - DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX) - -#define DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX) \ -void __attribute__((noinline)) \ -vec_sat_s_trunc_##NT##_##WT##_fmt_8 (NT *out, WT *in, unsigned limit) \ -{ \ - unsigned i; \ - for (i = 0; i < limit; i++) \ - { \ - WT x = in[i]; \ - NT trunc = (NT)x; \ - out[i] = (WT)NT_MIN >= x || x >= (WT)NT_MAX \ - ? x < 0 ? NT_MIN : NT_MAX \ - : trunc; \ - } \ -} -#define DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, NT_MIN, NT_MAX) \ - DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX) - -#define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \ - vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N) -#define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) - -#define RUN_VEC_SAT_U_TRUNC_FMT_2(NT, WT, out, in, N) \ - vec_sat_u_trunc_##NT##_##WT##_fmt_2 (out, in, N) -#define RUN_VEC_SAT_U_TRUNC_FMT_2_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_U_TRUNC_FMT_2(NT, WT, out, in, N) - -#define RUN_VEC_SAT_U_TRUNC_FMT_3(NT, WT, out, in, N) \ - vec_sat_u_trunc_##NT##_##WT##_fmt_3 (out, in, N) -#define RUN_VEC_SAT_U_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_U_TRUNC_FMT_3(NT, WT, out, in, N) - -#define RUN_VEC_SAT_U_TRUNC_FMT_4(NT, WT, out, in, N) \ - vec_sat_u_trunc_##NT##_##WT##_fmt_4 (out, in, N) -#define RUN_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_U_TRUNC_FMT_4(NT, WT, out, in, N) - -#define RUN_VEC_SAT_S_TRUNC_FMT_1(NT, WT, out, in, N) \ - vec_sat_s_trunc_##NT##_##WT##_fmt_1 (out, in, N) -#define RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_S_TRUNC_FMT_1(NT, WT, out, in, N) - -#define RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N) \ - vec_sat_s_trunc_##NT##_##WT##_fmt_2 (out, in, N) -#define RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N) - -#define RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N) \ - vec_sat_s_trunc_##NT##_##WT##_fmt_3 (out, in, N) -#define RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N) - -#define RUN_VEC_SAT_S_TRUNC_FMT_4(NT, WT, out, in, N) \ - vec_sat_s_trunc_##NT##_##WT##_fmt_4 (out, in, N) -#define RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_S_TRUNC_FMT_4(NT, WT, out, in, N) - -#define RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N) \ - vec_sat_s_trunc_##NT##_##WT##_fmt_5 (out, in, N) -#define RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N) - -#define RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N) \ - vec_sat_s_trunc_##NT##_##WT##_fmt_6 (out, in, N) -#define RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N) - -#define RUN_VEC_SAT_S_TRUNC_FMT_7(NT, WT, out, in, N) \ - vec_sat_s_trunc_##NT##_##WT##_fmt_7 (out, in, N) -#define RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_S_TRUNC_FMT_7(NT, WT, out, in, N) - -#define RUN_VEC_SAT_S_TRUNC_FMT_8(NT, WT, out, in, N) \ - vec_sat_s_trunc_##NT##_##WT##_fmt_8 (out, in, N) -#define RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, out, in, N) \ - RUN_VEC_SAT_S_TRUNC_FMT_8(NT, WT, out, in, N) - -#endif