From: Ju-Zhe Zhong Date: Mon, 6 Feb 2023 12:55:51 +0000 (+0800) Subject: RISC-V: Add vmulhsu.vx C++ API tests X-Git-Tag: basepoints/gcc-14~1342 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5a792199d80d7a780b1ec506e29a282a66bd554f;p=thirdparty%2Fgcc.git RISC-V: Add vmulhsu.vx C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C: New test. --- diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C new file mode 100644 index 000000000000..50fba59af464 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C new file mode 100644 index 000000000000..bb26e7420d17 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C new file mode 100644 index 000000000000..14fa0917de6a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C new file mode 100644 index 000000000000..d882f34f19d8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C new file mode 100644 index 000000000000..1e27032ee5a3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C new file mode 100644 index 000000000000..a85e843e4613 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C new file mode 100644 index 000000000000..8d875f983e87 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C new file mode 100644 index 000000000000..03feada95a1d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C new file mode 100644 index 000000000000..4b3c876016be --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C new file mode 100644 index 000000000000..81c3b26e34fa --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C new file mode 100644 index 000000000000..833d463bac28 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C new file mode 100644 index 000000000000..bb575d319eb5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C new file mode 100644 index 000000000000..febe18d4f0d4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C new file mode 100644 index 000000000000..672533c682a0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C new file mode 100644 index 000000000000..cd46ef1f6aa9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C new file mode 100644 index 000000000000..329a188285d4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C new file mode 100644 index 000000000000..43dfe69f8978 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C new file mode 100644 index 000000000000..66df249ce3d2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C new file mode 100644 index 000000000000..430b18b10c88 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C new file mode 100644 index 000000000000..0ddf21a6e0ad --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C new file mode 100644 index 000000000000..ab8a2ed74b9c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C new file mode 100644 index 000000000000..52942c45a68c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C new file mode 100644 index 000000000000..5dbd3b35e07b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C new file mode 100644 index 000000000000..80d6565ff643 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C new file mode 100644 index 000000000000..2c6cf9ca1e63 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C new file mode 100644 index 000000000000..f3fec8af9c6c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C new file mode 100644 index 000000000000..edbcb78e19a7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C new file mode 100644 index 000000000000..d3ffc1f3e4a0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C new file mode 100644 index 000000000000..1aa19f2b51f9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C new file mode 100644 index 000000000000..8c73d15b76dd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */