From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: Wed, 28 Apr 2021 14:16:53 +0000 (+0200)
Subject: hw/sparc64: Fix code style for checkpatch.pl
X-Git-Tag: v6.1.0-rc0~137^2~1
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5aa7f68a2df9604dbd7f95e9ecece6d553e46e32;p=thirdparty%2Fqemu.git

hw/sparc64: Fix code style for checkpatch.pl

We are going to move this code, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210428141655.387430-4-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---

diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index cc0b9bd30d3..fd29a79edc0 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env)
         return;
     }
     cs = env_cpu(env);
-    /* check if TM or SM in SOFTINT are set
-       setting these also causes interrupt 14 */
+    /*
+     * check if TM or SM in SOFTINT are set
+     * setting these also causes interrupt 14
+     */
     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
         pil |= 1 << 14;
     }
 
-    /* The bit corresponding to psrpil is (1<< psrpil), the next bit
-       is (2 << psrpil). */
+    /*
+     * The bit corresponding to psrpil is (1<< psrpil),
+     * the next bit is (2 << psrpil).
+     */
     if (pil < (2 << env->psrpil)) {
         if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
             trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);