From: Bing Niu <bing.niu@intel.com>
Date: Mon, 30 Jul 2018 03:12:29 +0000 (+0800)
Subject: util: Add MBA check to virResctrlInfoGetCache
X-Git-Tag: v4.7.0-rc1~183
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5aae2b3968c3e474e288cff68547f7aedac86921;p=thirdparty%2Flibvirt.git

util: Add MBA check to virResctrlInfoGetCache

If we have some membw_info data, then we need to calculate the number
of MBA controllers on the system. The value cannot be obtained from a
direct query to the RDT kernel module, but it is the same as the last
level cache value which is calculated by traversing the cache hierarchy
of host(/sys/bus/cpu/devices/cpuX/cache/).

Signed-off-by: Bing Niu <bing.niu@intel.com>
Reviewed-by: John Ferlan <jferlan@redhat.com>
---

diff --git a/src/util/virresctrl.c b/src/util/virresctrl.c
index b12a05cb0f..f454868f1e 100644
--- a/src/util/virresctrl.c
+++ b/src/util/virresctrl.c
@@ -608,6 +608,20 @@ virResctrlInfoGetCache(virResctrlInfoPtr resctrl,
     if (virResctrlInfoIsEmpty(resctrl))
         return 0;
 
+    /* Let's take the opportunity to update the number of last level
+     * cache. This number of memory bandwidth controller is same with
+     * last level cache */
+    if (resctrl->membw_info) {
+        virResctrlInfoMemBWPtr membw_info = resctrl->membw_info;
+
+        if (level > membw_info->last_level_cache) {
+            membw_info->last_level_cache = level;
+            membw_info->max_id = 0;
+        } else if (membw_info->last_level_cache == level) {
+            membw_info->max_id++;
+        }
+    }
+
     if (level >= resctrl->nlevels)
         return 0;