From: Patrick O'Neill Date: Tue, 19 Sep 2023 17:03:35 +0000 (-0700) Subject: RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap X-Git-Tag: basepoints/gcc-15~5985 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5b554c559d0103bfc1a68777907945ec3035a2bd;p=thirdparty%2Fgcc.git RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap Resolves PR 111461. during RTL pass: expand offtime.c: In function '__offtime': offtime.c:79:6: internal compiler error: RTL check: expected elt 0 type 'e' or 'u', have 'w' (rtx const_int) in riscv_legitimize_const_move, at config/riscv/riscv.cc:2176 79 | ip = __mon_yday[__isleap(y)]; Tested on rv32gc glibc with --enable-checking=rtl. 2023-09-19 Juzhe Zhong gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_const_move): Eliminate src_op_0 var to avoid rtl check error. Tested-by: Patrick O'Neill --- diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index f1b721d54d15..29d439b42827 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2173,16 +2173,14 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) (const_poly_int:DI [16, 16]) // <- op_1 )) */ - rtx src_op_0 = XEXP (src, 0); - - if (GET_CODE (src) == CONST && GET_CODE (src_op_0) == PLUS - && CONST_POLY_INT_P (XEXP (src_op_0, 1))) + if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS + && CONST_POLY_INT_P (XEXP (XEXP (src, 0), 1))) { rtx dest_tmp = gen_reg_rtx (mode); rtx tmp = gen_reg_rtx (mode); - riscv_emit_move (dest, XEXP (src_op_0, 0)); - riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (src_op_0, 1)); + riscv_emit_move (dest, XEXP (XEXP (src, 0), 0)); + riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (XEXP (src, 0), 1)); emit_insn (gen_rtx_SET (dest, gen_rtx_PLUS (mode, dest, dest_tmp))); return;