From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Fri, 26 May 2023 00:59:29 +0000 (+0800)
Subject: RISC-V: Fix zero-scratch-regs-3.c fail
X-Git-Tag: basepoints/gcc-15~8888
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5bd67d7abddca87198b11efccedee42f82e9f3a9;p=thirdparty%2Fgcc.git

RISC-V: Fix zero-scratch-regs-3.c fail

gcc/ChangeLog:

	* config/riscv/riscv.cc (vector_zero_call_used_regs): Add
	explict VL and drop VL in ops.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
---

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 09fc9e5d95e6..b16c60df6a75 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7396,9 +7396,9 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
 	      emitted_vlmax_vsetvl = true;
 	    }
 
-	  rtx ops[] = {target, CONST0_RTX (mode), vl};
+	  rtx ops[] = {target, CONST0_RTX (mode)};
 	  riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode),
-					 riscv_vector::RVV_UNOP, ops);
+					 riscv_vector::RVV_UNOP, ops, vl);
 
 	  SET_HARD_REG_BIT (zeroed_hardregs, regno);
 	}