From: Bill Schmidt Date: Fri, 20 Oct 2017 21:35:41 +0000 (+0000) Subject: backport: rs6000.c (rs6000_gen_le_vsx_permute): Use rotate instead of vec_select... X-Git-Tag: releases/gcc-6.5.0~725 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5cc5a804cb3f24e5aea918c353c5dad11bb28937;p=thirdparty%2Fgcc.git backport: rs6000.c (rs6000_gen_le_vsx_permute): Use rotate instead of vec_select for V1TImode. 2017-10-20 Bill Schmidt Backport from mainline 2017-03-09 Bill Schmidt * config/rs6000/rs6000.c (rs6000_gen_le_vsx_permute): Use rotate instead of vec_select for V1TImode. * conifg/rs6000/vsx.md (VSX_LE): Remove mode iterator that is no longer needed. (VSX_LE_128): Add V1TI to this mode iterator. (*vsx_le_perm_load_): Change to use VSX_D mode iterator. (*vsx_le_perm_store_): Likewise. (pre-reload splitter for VSX stores): Likewise. (post-reload splitter for VSX stores): Likewise. (*vsx_xxpermdi2_le_): Likewise. (*vsx_lxvd2x2_le_): Likewise. (*vsx_stxvd2x2_le_): Likewise. From-SVN: r253961 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 741988f715fd..f913083c3531 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2017-10-20 Bill Schmidt + + Backport from mainline + 2017-03-09 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_gen_le_vsx_permute): Use rotate + instead of vec_select for V1TImode. + * conifg/rs6000/vsx.md (VSX_LE): Remove mode iterator that is no + longer needed. + (VSX_LE_128): Add V1TI to this mode iterator. + (*vsx_le_perm_load_): Change to use VSX_D mode iterator. + (*vsx_le_perm_store_): Likewise. + (pre-reload splitter for VSX stores): Likewise. + (post-reload splitter for VSX stores): Likewise. + (*vsx_xxpermdi2_le_): Likewise. + (*vsx_lxvd2x2_le_): Likewise. + (*vsx_stxvd2x2_le_): Likewise. + 2017-10-19 Richard Earnshaw PR target/82445 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f6ea2c4cbf9a..07d69c431805 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -9591,7 +9591,7 @@ rs6000_gen_le_vsx_permute (rtx source, machine_mode mode) { /* Use ROTATE instead of VEC_SELECT on IEEE 128-bit floating point, and 128-bit integers if they are allowed in VSX registers. */ - if (FLOAT128_VECTOR_P (mode) || mode == TImode) + if (FLOAT128_VECTOR_P (mode) || mode == TImode || mode == V1TImode) return gen_rtx_ROTATE (mode, source, GEN_INT (64)); else { diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 358023b52d3e..d0715e951e62 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -24,15 +24,12 @@ ;; Iterator for the 2 64-bit vector types (define_mode_iterator VSX_D [V2DF V2DI]) -;; Iterator for the 2 64-bit vector types + 128-bit types that are loaded with -;; lxvd2x to properly handle swapping words on little endian -(define_mode_iterator VSX_LE [V2DF V2DI V1TI]) - ;; Mode iterator to handle swapping words on little endian for the 128-bit ;; types that goes in a single vector register. (define_mode_iterator VSX_LE_128 [(KF "FLOAT128_VECTOR_P (KFmode)") (TF "FLOAT128_VECTOR_P (TFmode)") - (TI "TARGET_VSX_TIMODE")]) + (TI "TARGET_VSX_TIMODE") + V1TI]) ;; Iterator for the 2 32-bit vector types (define_mode_iterator VSX_W [V4SF V4SI]) @@ -300,8 +297,8 @@ ;; The patterns for LE permuted loads and stores come before the general ;; VSX moves so they match first. (define_insn_and_split "*vsx_le_perm_load_" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=") - (match_operand:VSX_LE 1 "memory_operand" "Z"))] + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=") + (match_operand:VSX_D 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -414,16 +411,16 @@ (set_attr "length" "8")]) (define_insn "*vsx_le_perm_store_" - [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") - (match_operand:VSX_LE 1 "vsx_register_operand" "+"))] + [(set (match_operand:VSX_D 0 "memory_operand" "=Z") + (match_operand:VSX_D 1 "vsx_register_operand" "+"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") (set_attr "length" "12")]) (define_split - [(set (match_operand:VSX_LE 0 "memory_operand" "") - (match_operand:VSX_LE 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_D 0 "memory_operand" "") + (match_operand:VSX_D 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select: @@ -441,8 +438,8 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:VSX_LE 0 "memory_operand" "") - (match_operand:VSX_LE 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_D 0 "memory_operand" "") + (match_operand:VSX_D 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select: @@ -2003,9 +2000,9 @@ ;; xxpermdi for little endian loads and stores. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_xxpermdi2_le_" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=") - (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=") + (vec_select:VSX_D + (match_operand:VSX_D 1 "vsx_register_operand" "") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" "xxpermdi %x0,%x1,%x1,2" @@ -2052,9 +2049,9 @@ ;; lxvd2x for little endian loads. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_lxvd2x2_le_" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=") - (vec_select:VSX_LE - (match_operand:VSX_LE 1 "memory_operand" "Z") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=") + (vec_select:VSX_D + (match_operand:VSX_D 1 "memory_operand" "Z") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode) && !TARGET_P9_VECTOR" "lxvd2x %x0,%y1" @@ -2101,9 +2098,9 @@ ;; stxvd2x for little endian stores. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_stxvd2x2_le_" - [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") - (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "") + [(set (match_operand:VSX_D 0 "memory_operand" "=Z") + (vec_select:VSX_D + (match_operand:VSX_D 1 "vsx_register_operand" "") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode) && !TARGET_P9_VECTOR" "stxvd2x %x1,%y0"