From: Lad Prabhakar Date: Tue, 28 Oct 2025 17:54:55 +0000 (+0000) Subject: arm64: dts: renesas: r9a09g087: Add ETHSS node X-Git-Tag: v6.19-rc1~100^2~26^2~10 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5d06389a0587647bb44d65db01328b2fa85257da;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: renesas: r9a09g087: Add ETHSS node Add an Ethernet Switch Subsystem (ETHSS) device node to the RZ/N2H (R9A09G087) SoC. The ETHSS IP block is responsible for handling MII pass-through or conversion to RMII/RGMII. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251028175458.1037397-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 3ece794fb0a7c..fe0087a7d4b4e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -270,6 +270,43 @@ status = "disabled"; }; + ethss: ethss@80110000 { + compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic"; + reg = <0 0x80110000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G087_ETCLKE>, + <&cpg CPG_CORE R9A09G087_ETCLKB>, + <&cpg CPG_CORE R9A09G087_ETCLKD>, + <&cpg CPG_MOD 403>; + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + resets = <&cpg 405>, <&cpg 406>; + reset-names = "rst", "crst"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + mii_conv0: mii-conv@0 { + reg = <0>; + status = "disabled"; + }; + + mii_conv1: mii-conv@1 { + reg = <1>; + status = "disabled"; + }; + + mii_conv2: mii-conv@2 { + reg = <2>; + status = "disabled"; + }; + + mii_conv3: mii-conv@3 { + reg = <3>; + status = "disabled"; + }; + }; + cpg: clock-controller@80280000 { compatible = "renesas,r9a09g087-cpg-mssr"; reg = <0 0x80280000 0 0x1000>,