From: Jeff Law <jeffrey.law@oss.qualcomm.com>
Date: Wed, 31 Dec 2025 05:52:03 +0000 (-0700)
Subject: [RISC-V][PR target/121485] Fix mode on Zvkned lmul extending patterns
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5d3874416c5eb09d2de3d9bfa1f22f537c3384e2;p=thirdparty%2Fgcc.git

[RISC-V][PR target/121485] Fix mode on Zvkned lmul extending patterns

This fixes the mode on the lmul-extending variants of various Zvkned patterns.

Essentially vsetvl insertion depends on the mode of each insn and for lmul
extending patterns, we need the larger mode, not the smaller one to get the
correct vsetvls.

Tested on riscv{32,64}-elf on the simple testcase in the PR.  I also verified
the larger testcase in godbolt appears to work correctly.

Waiting on upstream CI before committing.

	PR target/121485
gcc/
	* config/riscv/vector-crypto.md: Fix mode attribute for the
	lmul extending Zvkned patterns.

gcc/testsuite/
	* gcc.target/riscv/rvv/vsetvl/pr121485.c: New test.
---

diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
index b3e6804f959..cd2e8807275 100644
--- a/gcc/config/riscv/vector-crypto.md
+++ b/gcc/config/riscv/vector-crypto.md
@@ -538,7 +538,7 @@
   "TARGET_ZVKNED || TARGET_ZVKSED"
   "v<vv_ins_name>.<ins_type>\t%0,%2"
   [(set_attr "type" "v<vv_ins_name>")
-   (set_attr "mode" "<MODE>")])
+   (set_attr "mode" "<V_VLSI_S_X2>")])
 
 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x4<mode>_scalar"
  [(set (match_operand:<V_VLSI_S_X4> 0 "register_operand"      "=&vr")
@@ -556,7 +556,7 @@
  "TARGET_ZVKNED || TARGET_ZVKSED"
  "v<vv_ins_name>.<ins_type>\t%0,%2"
  [(set_attr "type" "v<vv_ins_name>")
-  (set_attr "mode" "<MODE>")])
+  (set_attr "mode" "<V_VLSI_S_X4>")])
 
 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x8<mode>_scalar"
  [(set (match_operand:<V_VLSI_S_X8> 0 "register_operand"      "=&vr")
@@ -574,7 +574,7 @@
  "TARGET_ZVKNED || TARGET_ZVKSED"
  "v<vv_ins_name>.<ins_type>\t%0,%2"
  [(set_attr "type" "v<vv_ins_name>")
-  (set_attr "mode" "<MODE>")])
+  (set_attr "mode" "<V_VLSI_S_X8>")])
 
 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x16<mode>_scalar"
  [(set (match_operand:<V_VLSI_S_X16> 0 "register_operand"      "=&vr")
@@ -592,7 +592,7 @@
  "TARGET_ZVKNED || TARGET_ZVKSED"
  "v<vv_ins_name>.<ins_type>\t%0,%2"
  [(set_attr "type" "v<vv_ins_name>")
-  (set_attr "mode" "<MODE>")])
+  (set_attr "mode" "<V_VLSI_S_X16>")])
 
 ;; vaeskf1.vi vsm4k.vi
 (define_insn "@pred_crypto_vi<vi_ins_name><mode>_scalar"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr121485.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr121485.c
new file mode 100644
index 00000000000..2e066765211
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr121485.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvkned -mabi=lp64d" { target rv64 } } */
+/* { dg-options "-march=rv32gcv_zvkned -mabi=ilp32" { target rv32 } } */
+
+#include <riscv_vector.h>
+
+vuint32m4_t test_riscv_vaesz_vs_u32m1_u32m4(vuint32m4_t a, vuint32m1_t b, int vl)
+{
+  return __riscv_vaesz_vs_u32m1_u32m4(a, b, vl);
+}
+
+
+/* { dg-final { scan-assembler {vsetvli\szero,[a-x0-9]+,e32,m4,ta,ma} } } */