From: Tom St Denis Date: Tue, 2 Dec 2025 15:05:51 +0000 (-0500) Subject: drm/amd/amdgpu: Port over some missing registers and bits from GC 10.1 to 10.3 (v2) X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5e213a985d103ecd348ed4e9ae71292d86be9a71;p=thirdparty%2Fkernel%2Flinux.git drm/amd/amdgpu: Port over some missing registers and bits from GC 10.1 to 10.3 (v2) v2: Added SPI bits to sh_mask header Signed-off-by: Tom St Denis Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h index 5e15ac14b63c..3645266a2bcb 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h @@ -4493,6 +4493,8 @@ #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 #define mmGB_EDC_MODE 0x1e1e #define mmGB_EDC_MODE_BASE_IDX 0 +#define mmCP_DEBUG 0x1e1f +#define mmCP_DEBUG_BASE_IDX 0 #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23 #define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 #define mmCP_PQ_WPTR_POLL_CNTL1 0x1e24 @@ -5155,6 +5157,8 @@ #define mmTCP_WATCH3_ADDR_L_BASE_IDX 0 #define mmTCP_WATCH3_CNTL 0x204b #define mmTCP_WATCH3_CNTL_BASE_IDX 0 +#define mmTCP_UTCL0_STATUS 0x2057 +#define mmTCP_UTCL0_STATUS_BASE_IDX 0 #define mmTCP_PERFCOUNTER_FILTER 0x2059 #define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0 #define mmTCP_PERFCOUNTER_FILTER_EN 0x205a @@ -6951,6 +6955,8 @@ #define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 #define mmCP_CE_IB2_CMD_BUFSZ 0x20bf #define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 +#define mmCP_IB1_CMD_BUFSZ 0x20c0 +#define mmCP_IB1_CMD_BUFSZ_BASE_IDX 1 #define mmCP_IB2_CMD_BUFSZ 0x20c1 #define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1 #define mmCP_ST_CMD_BUFSZ 0x20c2 @@ -7413,6 +7419,8 @@ #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 #define mmCP_MES_DOORBELL_CONTROL6 0x2841 #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842 +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1 #define mmCP_MES_GP0_LO 0x2843 #define mmCP_MES_GP0_LO_BASE_IDX 1 #define mmCP_MES_GP0_HI 0x2844 @@ -9140,10 +9148,16 @@ #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1 #define mmRLC_LB_CNTR_1 0x4c1c #define mmRLC_LB_CNTR_1_BASE_IDX 1 +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1 #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 #define mmRLC_PG_DELAY_2 0x4c1f #define mmRLC_PG_DELAY_2_BASE_IDX 1 +#define mmRLC_GPM_DEBUG_INST_A 0x4c22 +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1 +#define mmRLC_GPM_DEBUG_INST_B 0x4c23 +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1 #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24 #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25 @@ -9608,6 +9622,8 @@ #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1 #define mmRLC_LB_CNTR_2 0x4de7 #define mmRLC_LB_CNTR_2_BASE_IDX 1 +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1 #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1 #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1 #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h index e4ecd6c2d20e..dde32271fb86 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h @@ -18054,6 +18054,23 @@ #define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L #define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL +//SPI_GDBG_TRAP_CONFIG +#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L //SPI_GDBG_TRAP_MASK #define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 #define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 @@ -19076,6 +19093,13 @@ #define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L #define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L #define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L +//TCP_UTCL0_STATUS +#define TCP_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define TCP_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define TCP_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define TCP_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define TCP_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define TCP_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L //TCP_PERFCOUNTER_FILTER #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 @@ -25836,6 +25860,9 @@ //CP_CE_IB1_CMD_BUFSZ #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB1_CMD_BUFSZ +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL //CP_CE_IB2_CMD_BUFSZ #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL