From: Jiufu Guo <guojiufu@linux.ibm.com>
Date: Thu, 28 Sep 2023 09:00:04 +0000 (+0800)
Subject: rs6000: optimize moving to sf from highpart di
X-Git-Tag: basepoints/gcc-15~5695
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5f56b76ff1c15118200204569389f85cca4e32d3;p=thirdparty%2Fgcc.git

rs6000: optimize moving to sf from highpart di

Currently, we have the pattern "movsf_from_si2" which was trying
to support moving high part DI to SF.

But current pattern only accepts "ashiftrt":
XX:SF=bitcast:SF(subreg(YY:DI>>32),0), but actually "lshiftrt" should
also be ok.
And current pattern only supports BE.

Here, updating the pattern to support BE and "lshiftrt".

	PR target/108338

gcc/ChangeLog:

	* config/rs6000/predicates.md (lowpart_subreg_operator): New
	define_predicate.
	* config/rs6000/rs6000.md (any_rshift): New code_iterator.
	(movsf_from_si2): Rename to ...
	(movsf_from_si2_<code>): ... this.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/pr108338.c: New test.
---

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 925f69cd3fca..ef7d3f214c42 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -2098,3 +2098,8 @@
   else
     return false;
 })
+
+(define_predicate "lowpart_subreg_operator"
+  (and (match_code "subreg")
+       (match_test "subreg_lowpart_offset (mode, GET_MODE (SUBREG_REG (op)))
+		    == SUBREG_BYTE (op)")))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d3ebca00757c..8e7edfc0a2df 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -642,6 +642,9 @@
 (define_code_iterator any_fix		[fix unsigned_fix])
 (define_code_iterator any_float		[float unsigned_float])
 
+; Shift right.
+(define_code_iterator any_shiftrt	[ashiftrt lshiftrt])
+
 (define_code_attr u  [(sign_extend	"")
 		      (zero_extend	"u")
 		      (fix		"")
@@ -8329,14 +8332,13 @@
 ;;     {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}
 ;; split it before reload with "and mask" to avoid generating shift right
 ;; 32 bit then shift left 32 bit.
-(define_insn_and_split "movsf_from_si2"
+(define_insn_and_split "movsf_from_si2_<code>"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
 	    (unspec:SF
-	     [(subreg:SI
-	       (ashiftrt:DI
+	     [(match_operator:SI 3 "lowpart_subreg_operator"
+	       [(any_shiftrt:DI
 		(match_operand:DI 1 "input_operand" "r")
-		(const_int 32))
-	       0)]
+		(const_int 32))])]
 	     UNSPEC_SF_FROM_SI))
   (clobber (match_scratch:DI 2 "=r"))]
   "TARGET_NO_SF_SUBREG"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c b/gcc/testsuite/gcc.target/powerpc/pr108338.c
new file mode 100644
index 000000000000..bd83c0b3ad84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */
+/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
+/* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
+
+struct di_sf_sf
+{
+  float f1; float f2; long long l;
+};
+
+float __attribute__ ((noipa))
+sf_from_high32bit_di (struct di_sf_sf v)
+{
+#ifdef __LITTLE_ENDIAN__
+  return v.f2;
+#else
+  return v.f1;
+#endif
+}
+
+int main()
+{
+  struct di_sf_sf v;
+  v.f1 = v.f2 = 0.0f;
+#ifdef __LITTLE_ENDIAN__
+  v.f2 = 2.0f;
+#else
+  v.f1 = 2.0f;
+#endif
+  if (sf_from_high32bit_di (v) != 2.0f)
+    __builtin_abort ();
+  return 0;
+}