From: Tom Hughes <tom@compton.nu>
Date: Thu, 11 Aug 2011 14:43:12 +0000 (+0000)
Subject: Support FEMMS in x86 mode as we already do for amd64. Fix for #204574.
X-Git-Tag: svn/VALGRIND_3_7_0^2~32
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=605c89671d2a7dcfce6f5d2bab7320ea15c0aeee;p=thirdparty%2Fvalgrind.git

Support FEMMS in x86 mode as we already do for amd64. Fix for #204574.

Note, from #124499 where this was discussed for amd64, that FEMMS is
a 3DNow instruction that has identical behaviour to EMMS and is only
supposed on AMD processors for backwards compatibility.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2192
---

diff --git a/VEX/priv/guest_x86_toIR.c b/VEX/priv/guest_x86_toIR.c
index 3f5bf9191e..41481b6b6e 100644
--- a/VEX/priv/guest_x86_toIR.c
+++ b/VEX/priv/guest_x86_toIR.c
@@ -15006,11 +15006,12 @@ DisResult disInstr_X86_WRK (
          break;
       }
 
+      case 0x0E: /* FEMMS */
       case 0x77: /* EMMS */
          if (sz != 4)
             goto decode_failure;
          do_EMMS_preamble();
-         DIP("emms\n");
+         DIP("{f}emms\n");
          break;
 
       /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */