From: Mike Pall <mike>
Date: Fri, 9 Dec 2011 23:18:19 +0000 (+0100)
Subject: ARM: Fix stack check for spilled BASE in parent.
X-Git-Tag: v2.0.0-beta9~7
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=60b8e9e2fbc2df3281bc9fac714aad3fd7578717;p=thirdparty%2FLuaJIT.git

ARM: Fix stack check for spilled BASE in parent.
---

diff --git a/src/lj_asm_arm.h b/src/lj_asm_arm.h
index 0ab4917e..24b49e69 100644
--- a/src/lj_asm_arm.h
+++ b/src/lj_asm_arm.h
@@ -1422,8 +1422,9 @@ static void asm_stack_check(ASMState *as, BCReg topslot,
   Reg pbase;
   uint32_t k;
   if (irp) {
-    if (ra_hasreg(irp->r)) {
+    if (!ra_hasspill(irp->s)) {
       pbase = irp->r;
+      lua_assert(ra_hasreg(pbase));
     } else if (allow) {
       pbase = rset_pickbot(allow);
     } else {
@@ -1442,14 +1443,11 @@ static void asm_stack_check(ASMState *as, BCReg topslot,
 	   (int32_t)offsetof(lua_State, maxstack));
   if (irp) {  /* Must not spill arbitrary registers in head of side trace. */
     int32_t i = i32ptr(&J2G(as->J)->jit_L);
-    if (ra_noreg(irp->r)) {
-      lua_assert(ra_hasspill(irp->s));
-      emit_lso(as, ARMI_LDR, RID_RET, RID_SP, sps_scale(irp->s));
-    }
+    if (ra_hasspill(irp->s))
+      emit_lso(as, ARMI_LDR, pbase, RID_SP, sps_scale(irp->s));
     emit_lso(as, ARMI_LDR, RID_TMP, RID_TMP, (i & 4095));
-    if (ra_noreg(irp->r)) {
+    if (ra_hasspill(irp->s) && !allow)
       emit_lso(as, ARMI_STR, RID_RET, RID_SP, 0);  /* Save temp. register. */
-    }
     emit_loadi(as, RID_TMP, (i & ~4095));
   } else {
     emit_getgl(as, RID_TMP, jit_L);