From: Anup Patel Date: Mon, 10 Jul 2023 13:19:02 +0000 (+0530) Subject: clocksource: timer-riscv: Increase rating of clock_event_device for Sstc X-Git-Tag: v6.7-rc1~38^2~12 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=60c46877e9cd4f7fd13fa844258f60cca4eb3e34;p=thirdparty%2Fkernel%2Fstable.git clocksource: timer-riscv: Increase rating of clock_event_device for Sstc When Sstc is available the RISC-V timer clock_event_device should be the preferred clock_event_device hence we increase clock_event_device rating for Sstc. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20230710131902.1459180-3-apatel@ventanamicro.com Signed-off-by: Palmer Dabbelt --- diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index f2ea2b3d2d43e..9c8f3e2decc22 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -105,6 +105,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu) ce->irq = riscv_clock_event_irq; if (riscv_timer_cannot_wake_cpu) ce->features |= CLOCK_EVT_FEAT_C3STOP; + if (static_branch_likely(&riscv_sstc_available)) + ce->rating = 450; clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); enable_percpu_irq(riscv_clock_event_irq,