From: Dejan Jevtic Date: Mon, 7 Oct 2013 10:28:56 +0000 (+0000) Subject: mips64: add extra Iop cases in VEX. X-Git-Tag: svn/VALGRIND_3_9_0^2~12 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=615f81bd693ab831efabca45b5549cec887cfc62;p=thirdparty%2Fvalgrind.git mips64: add extra Iop cases in VEX. git-svn-id: svn://svn.valgrind.org/vex/trunk@2783 --- diff --git a/VEX/priv/host_mips_defs.c b/VEX/priv/host_mips_defs.c index 215efbcc97..1127e677c2 100644 --- a/VEX/priv/host_mips_defs.c +++ b/VEX/priv/host_mips_defs.c @@ -3960,6 +3960,11 @@ Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_profInc, fr_src = dregNo(i->Min.FpConvert.src); p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x0F); break; + case Mfp_FLOORLD: + fr_dst = dregNo(i->Min.FpConvert.dst); + fr_src = dregNo(i->Min.FpConvert.src); + p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x0B); + break; default: goto bad; diff --git a/VEX/priv/host_mips_defs.h b/VEX/priv/host_mips_defs.h index bccb0c91bf..dceb892b98 100644 --- a/VEX/priv/host_mips_defs.h +++ b/VEX/priv/host_mips_defs.h @@ -367,7 +367,7 @@ typedef enum { Mfp_CVTWS, Mfp_CVTDL, Mfp_CVTSL, Mfp_CVTLS, Mfp_CVTLD, Mfp_TRULS, Mfp_TRULD, Mfp_TRUWS, Mfp_TRUWD, Mfp_FLOORWS, Mfp_FLOORWD, Mfp_ROUNDWS, Mfp_ROUNDWD, Mfp_CVTDW, Mfp_CMP, Mfp_CEILWS, Mfp_CEILWD, Mfp_CEILLS, Mfp_CEILLD, - Mfp_CVTDS, Mfp_ROUNDLD + Mfp_CVTDS, Mfp_ROUNDLD, Mfp_FLOORLD } MIPSFpOp; diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c index 9bd4b3e54f..266e27574c 100644 --- a/VEX/priv/host_mips_isel.c +++ b/VEX/priv/host_mips_isel.c @@ -836,6 +836,8 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) aluOp = Malu_DSUB; break; + case Iop_And8: + case Iop_And16: case Iop_And32: case Iop_And64: aluOp = Malu_AND; @@ -848,6 +850,8 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) aluOp = Malu_OR; break; + case Iop_Xor8: + case Iop_Xor16: case Iop_Xor32: case Iop_Xor64: aluOp = Malu_XOR; @@ -1364,6 +1368,7 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) case Iop_1Sto8: case Iop_1Sto16: case Iop_1Sto32: + case Iop_8Sto16: case Iop_8Sto32: case Iop_16Sto32: case Iop_16Sto64: @@ -1394,6 +1399,10 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) amt = 48; sz32 = False; break; + case Iop_8Sto16: + amt = 24; + sz32 = True; + break; case Iop_8Sto32: amt = 24; sz32 = True; @@ -1484,11 +1493,10 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) } case Iop_16to8: + case Iop_32to1: case Iop_32to8: case Iop_32to16: return iselWordExpr_R(env, e->Iex.Unop.arg); - case Iop_32to1: - return iselWordExpr_R(env, e->Iex.Unop.arg); case Iop_32HIto16: { HReg r_dst = newVRegI(env); @@ -1498,13 +1506,15 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) return r_dst; } + case Iop_64to1: case Iop_64to8: { vassert(mode64); HReg r_src, r_dst; + UShort mask = (op_unop == Iop_64to1) ? 0x1 : 0xFF; r_dst = newVRegI(env); r_src = iselWordExpr_R(env, e->Iex.Unop.arg); addInstr(env, MIPSInstr_Alu(Malu_AND, r_dst, r_src, - MIPSRH_Imm(False, 0xFF))); + MIPSRH_Imm(False, mask))); return r_dst; } @@ -1516,6 +1526,7 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) return r_dst; } + case Iop_1Uto8: case Iop_1Uto32: case Iop_1Uto64: case Iop_8Uto16: @@ -1529,6 +1540,7 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) switch (op_unop) { case Iop_1Uto64: vassert(mode64); + case Iop_1Uto8: case Iop_1Uto32: mask = toUShort(0x1); break; @@ -2201,22 +2213,21 @@ static void iselInt128Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env, switch (e->Iex.Binop.op) { /* 64 x 64 -> 128 multiply */ case Iop_MullU64: - case Iop_MullS64: - { - HReg tLo = newVRegI(env); - HReg tHi = newVRegI(env); - Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64); - HReg r_dst = newVRegI(env); - HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); - HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2); - addInstr(env, MIPSInstr_Mul(syned, True, False /*64bit mul */ , - r_dst, r_srcL, r_srcR)); - addInstr(env, MIPSInstr_Mfhi(tHi)); - addInstr(env, MIPSInstr_Mflo(tLo)); - *rHi = tHi; - *rLo = tLo; - return; - } + case Iop_MullS64: { + HReg tLo = newVRegI(env); + HReg tHi = newVRegI(env); + Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64); + HReg r_dst = newVRegI(env); + HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); + HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2); + addInstr(env, MIPSInstr_Mul(syned, True, False /*64bit mul */ , + r_dst, r_srcL, r_srcR)); + addInstr(env, MIPSInstr_Mfhi(tHi)); + addInstr(env, MIPSInstr_Mflo(tLo)); + *rHi = tHi; + *rLo = tLo; + return; + } /* 64HLto128(e1,e2) */ case Iop_64HLto128: @@ -2239,7 +2250,8 @@ static void iselInt128Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env, return; } - case Iop_DivModU128to64: { + case Iop_DivModU128to64: + case Iop_DivModS128to64: { vassert(mode64); HReg rHi1, rLo1; iselInt128Expr(&rHi1, &rLo1, env, e->Iex.Binop.arg1); @@ -2952,6 +2964,28 @@ static HReg iselFltExpr_wrk(ISelEnv * env, IRExpr * e) addInstr(env, MIPSInstr_FpConvert(Mfp_TRULD, dst, src)); return dst; } + case Iop_RoundF64toF64_NEAREST: { + vassert(mode64); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegF(env); + addInstr(env, MIPSInstr_FpConvert(Mfp_ROUNDLD, dst, src)); + return dst; + } + case Iop_RoundF64toF64_NegINF: { + vassert(mode64); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegF(env); + addInstr(env, MIPSInstr_FpConvert(Mfp_FLOORLD, dst, src)); + return dst; + } + case Iop_RoundF64toF64_PosINF: { + vassert(mode64); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegF(env); + addInstr(env, MIPSInstr_FpConvert(Mfp_CEILLD, dst, src)); + return dst; + } + default: break; } @@ -3349,7 +3383,7 @@ static HReg iselDblExpr_wrk(ISelEnv * env, IRExpr * e) return valD1; } - case Iop_SqrtF64:{ + case Iop_SqrtF64: { /* first arg is rounding mode; we ignore it. */ HReg src = iselDblExpr(env, e->Iex.Binop.arg2); HReg dst = newVRegD(env);