From: Juzhe-Zhong Date: Mon, 19 Jun 2023 23:04:06 +0000 (+0800) Subject: RISC-V: Fix fails of testcases X-Git-Tag: basepoints/gcc-15~8182 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=62514099cb56574d96e29e2688aca23eeba5268f;p=thirdparty%2Fgcc.git RISC-V: Fix fails of testcases FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess errors) Excess errors: xgcc: fatal error: Cannot find suitable multilib set for '-march=rv64imafdcv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b'/'-mabi=lp64d' compilation terminated. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: Fix fail. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c: Ditto. --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c index 82bf6d674ecd..dd22dae5eb9a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv -Wno-pedantic" } */ +/* { dg-additional-options "-std=c99 -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c index a0b2cf97afe2..db54acc6535c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run {target { riscv_zvfh_hw } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */ +/* { dg-additional-options "-Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c index 7e5e0e69d51a..bf04a3d029ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_vector } } } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv -Wno-pedantic" } */ +/* { dg-additional-options "-std=c99 -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c index bf514f9426b8..df8363e04286 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh_hw } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */ +/* { dg-additional-options "-Wno-pedantic" } */ #include