From: Petar Jovanovic <mips32r2@gmail.com>
Date: Wed, 3 Sep 2014 14:39:56 +0000 (+0000)
Subject: mips64: implement Cavium BBIT0 and BBIT1 instructions
X-Git-Tag: svn/VALGRIND_3_10_1^2~30
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=62c0e6c634d32daef68265c0e3dd8a84b5e70514;p=thirdparty%2Fvalgrind.git

mips64: implement Cavium BBIT0 and BBIT1 instructions

Implement Cavium specific instructions:
- BBIT0 (Branch on bit clear)
- BBIT1 (Branch on bit set)

This should fix the hang issue reported in:
https://bugs.kde.org/show_bug.cgi?id=336139


git-svn-id: svn://svn.valgrind.org/vex/trunk@2942
---

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index db04ad4f37..908f2c83fd 100644
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -774,6 +774,11 @@ static Bool branch_or_jump(UChar * addr)
       return True;
    }
 
+   /* Cavium Specific instructions. */
+   if (opcode == 0x32 || opcode == 0x3A) {  /* BBIT0, BBIT1 */
+      return True;
+   }
+
    return False;
 }
 
@@ -17086,6 +17091,47 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
       store(mkexpr(t1), getIReg(rt));
       break;
 
+   case 0x32:  /* Branch on Bit Clear - BBIT0; Cavium OCTEON */
+      /* Cavium Specific instructions. */
+      if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM) {
+         DIP("bbit0 r%d, 0x%x, %x", rs, rt, imm);
+         t0 = newTemp(Ity_I32);
+         t1 = newTemp(Ity_I32);
+         assign(t0, mkU32(0x1));
+         assign(t1, binop(Iop_Shl32, mkexpr(t0), mkU8(rt)));
+         dis_branch(False, binop(Iop_CmpEQ32,
+                                 binop(Iop_And32,
+                                       mkexpr(t1),
+                                       mkNarrowTo32(ty, getIReg(rs))),
+                                 mkU32(0x0)),
+                    imm, &bstmt);
+         break;
+      } else {
+         goto decode_failure;
+      }
+
+   case 0x3A:  /* Branch on Bit Set - BBIT1; Cavium OCTEON */
+      /* Cavium Specific instructions. */
+      if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM) {
+         DIP("bbit1 r%d, 0x%x, %x", rs, rt, imm);
+         t0 = newTemp(Ity_I32);
+         t1 = newTemp(Ity_I32);
+         assign(t0, mkU32(0x1));
+         assign(t1, binop(Iop_Shl32, mkexpr(t0), mkU8(rt)));
+         dis_branch(False, binop(Iop_CmpNE32,
+                                 binop(Iop_And32,
+                                       mkexpr(t1),
+                                       mkNarrowTo32(ty, getIReg(rs))),
+                                 mkU32(0x0)),
+                    imm, &bstmt);
+         break;
+      } else {
+         goto decode_failure;
+      }
+
+   default:
+      goto decode_failure;
+
    decode_failure_dsp:
       vex_printf("Error occured while trying to decode MIPS32 DSP "
                  "instruction.\nYour platform probably doesn't support "