From: Konrad Dybcio Date: Mon, 3 Feb 2025 14:43:23 +0000 (+0100) Subject: arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets X-Git-Tag: v6.16-rc1~97^2~20^2~115^2~156 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=62ca6669d62eb554eb467f2953cabb4238e18823;p=thirdparty%2Fkernel%2Fstable.git arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets Asserting the NOCSR reset line keeps the PHY registers in tact. This allows us to avoid programming long tables of magic values in the operating system. Wire up these resets to PCIe PHY4 and 5 (it's there on the others). Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-4-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index b927a77727010..62fa05210f68d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3558,8 +3558,10 @@ "pipe", "pipediv2"; - resets = <&gcc GCC_PCIE_5_PHY_BCR>; - reset-names = "phy"; + resets = <&gcc GCC_PCIE_5_PHY_BCR>, + <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; @@ -3692,8 +3694,10 @@ "pipe", "pipediv2"; - resets = <&gcc GCC_PCIE_4_PHY_BCR>; - reset-names = "phy"; + resets = <&gcc GCC_PCIE_4_PHY_BCR>, + <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>;