From: Quentin Schulz Date: Tue, 18 Feb 2025 11:49:12 +0000 (+0100) Subject: arm64: dts: rockchip: enable UART5 on RK3588 Tiger Haikou X-Git-Tag: v6.15-rc1~159^2~23^2~50 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=62deeee28921dafdb8e55e72842e5900a57dac55;p=thirdparty%2Flinux.git arm64: dts: rockchip: enable UART5 on RK3588 Tiger Haikou In its default configuration (SW2 on "UART1"), UART5 is exposed on the DB9 RS232/RS485 connector. While the same signals are also exposed on Q7_GPIO5 and Q7_GPIO6, a GPIO header, and thus could be used for other purposes, RK3399 Puma Haikou and PX30 Ringneck Haikou do enable the UART controller exposed on the DB9 connector, so let's keep consistency across our modules and enable it on RK3588 Tiger Haikou by default too. Add a comment while at it to explicit where this controller is routed to. Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-1-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner --- diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index 795d8175e6542..a3d8ff647839a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -310,8 +310,10 @@ status = "okay"; }; +/* DB9 RS232/RS485 when SW2 in "UART1" mode */ &uart5 { rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; }; &usbdp_phy0 {