From: Dejan Jevtic Date: Mon, 2 Sep 2013 15:35:12 +0000 (+0000) Subject: mips32/mips64: Add tests for lwl and lwr for mips32 and mips64. X-Git-Tag: svn/VALGRIND_3_9_0~165 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=63d3dd83511b26c71d34b77e43aacb4fa80cade5;p=thirdparty%2Fvalgrind.git mips32/mips64: Add tests for lwl and lwr for mips32 and mips64. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13526 --- diff --git a/none/tests/mips32/Makefile.am b/none/tests/mips32/Makefile.am index b11e973254..ebf53c775a 100644 --- a/none/tests/mips32/Makefile.am +++ b/none/tests/mips32/Makefile.am @@ -28,7 +28,9 @@ EXTRA_DIST = \ mips32_dsp.stdout.exp-mips32 mips32_dsp.stderr.exp \ mips32_dsp.vgtest \ mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \ - mips32_dspr2.stdout.exp-mips32 mips32_dspr2.vgtest + mips32_dspr2.stdout.exp-mips32 mips32_dspr2.vgtest \ + unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \ + unaligned_load_store.stderr.exp unaligned_load_store.vgtest check_PROGRAMS = \ allexec \ @@ -45,7 +47,8 @@ check_PROGRAMS = \ SignalException \ bug320057-mips32 \ mips32_dsp \ - mips32_dspr2 + mips32_dspr2 \ + unaligned_load_store AM_CFLAGS += @FLAG_M32@ AM_CXXFLAGS += @FLAG_M32@ diff --git a/none/tests/mips32/unaligned_load_store.c b/none/tests/mips32/unaligned_load_store.c new file mode 100644 index 0000000000..ac6af1f95d --- /dev/null +++ b/none/tests/mips32/unaligned_load_store.c @@ -0,0 +1,67 @@ +#include +unsigned int mem[] = { + 0xaabbccdd, 0x11223344, 0x01823194, 0x01823a08, + 0x00000000, 0x77ff528c, 0x77deb460, 0x00000001 +}; + +void printMem(char* s) +{ + int i; + printf("%s\n", s); + for (i=0; i<7 ; i=i+1) + printf("mem[%d]: 0x%x\n", i, mem[i]); +} + +int main () +{ + printMem("PRE lwl"); + __asm__ volatile("move $a0, %0" "\n\t" + "lw $t0, 0($a0)" "\n\t" + "lwl $t0, 4($a0)" "\n\t" + "sw $t0, 8($a0)" "\n\t" + "lw $t1, 0($a0)" "\n\t" + "lwl $t1, 5($a0)" "\n\t" + "sw $t1, 12($a0)" "\n\t" + "lw $t2, 0($a0)" "\n\t" + "lwl $t2, 6($a0)" "\n\t" + "sw $t2, 16($a0)" "\n\t" + "lw $t3, 0($a0)" "\n\t" + "lwl $t3, 7($a0)" "\n\t" + "sw $t3, 20($a0)" "\n\t" + : + : "r" (mem) + : "a0", "t0", "t1", "t2", "t3", "cc", "memory" + ); + printMem("POST lwl"); + + mem[0] = 0xaabbccdd; + mem[1] = 0x11223344; + mem[2] = 0x01823194; + mem[3] = 0x01823a08; + mem[4] = 0x00000000; + mem[5] = 0x77ff528c; + mem[6] = 0x77deb460; + mem[7] = 0x00000001; + + printMem("PRE lwr"); + __asm__ volatile("move $a0, %0" "\n\t" + "lw $t0, 0($a0)" "\n\t" + "lwr $t0, 4($a0)" "\n\t" + "sw $t0, 8($a0)" "\n\t" + "lw $t1, 0($a0)" "\n\t" + "lwr $t1, 5($a0)" "\n\t" + "sw $t1, 12($a0)" "\n\t" + "lw $t2, 0($a0)" "\n\t" + "lwr $t2, 6($a0)" "\n\t" + "sw $t2, 16($a0)" "\n\t" + "lw $t3, 0($a0)" "\n\t" + "lwr $t3, 7($a0)" "\n\t" + "sw $t3, 20($a0)" "\n\t" + : + : "r" (mem) + : "a0", "t0", "t1", "t2", "t3", "cc", "memory" + ); + printMem("POST lwr"); + + return 0; +} diff --git a/none/tests/mips32/unaligned_load_store.stderr.exp b/none/tests/mips32/unaligned_load_store.stderr.exp new file mode 100644 index 0000000000..e69de29bb2 diff --git a/none/tests/mips32/unaligned_load_store.stdout.exp-BE b/none/tests/mips32/unaligned_load_store.stdout.exp-BE new file mode 100644 index 0000000000..d8c6fee51c --- /dev/null +++ b/none/tests/mips32/unaligned_load_store.stdout.exp-BE @@ -0,0 +1,32 @@ +PRE lwl +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x1823194 +mem[3]: 0x1823a08 +mem[4]: 0x0 +mem[5]: 0x77ff528c +mem[6]: 0x77deb460 +POST lwl +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x11223344 +mem[3]: 0x223344dd +mem[4]: 0x3344ccdd +mem[5]: 0x44bbccdd +mem[6]: 0x77deb460 +PRE lwr +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x1823194 +mem[3]: 0x1823a08 +mem[4]: 0x0 +mem[5]: 0x77ff528c +mem[6]: 0x77deb460 +POST lwr +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0xaabbcc11 +mem[3]: 0xaabb1122 +mem[4]: 0xaa112233 +mem[5]: 0x11223344 +mem[6]: 0x77deb460 diff --git a/none/tests/mips32/unaligned_load_store.stdout.exp-LE b/none/tests/mips32/unaligned_load_store.stdout.exp-LE new file mode 100644 index 0000000000..fbf3b40528 --- /dev/null +++ b/none/tests/mips32/unaligned_load_store.stdout.exp-LE @@ -0,0 +1,32 @@ +PRE lwl +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x1823194 +mem[3]: 0x1823a08 +mem[4]: 0x0 +mem[5]: 0x77ff528c +mem[6]: 0x77deb460 +POST lwl +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x44bbccdd +mem[3]: 0x3344ccdd +mem[4]: 0x223344dd +mem[5]: 0x11223344 +mem[6]: 0x77deb460 +PRE lwr +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x1823194 +mem[3]: 0x1823a08 +mem[4]: 0x0 +mem[5]: 0x77ff528c +mem[6]: 0x77deb460 +POST lwr +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x11223344 +mem[3]: 0xaa112233 +mem[4]: 0xaabb1122 +mem[5]: 0xaabbcc11 +mem[6]: 0x77deb460 diff --git a/none/tests/mips32/unaligned_load_store.vgtest b/none/tests/mips32/unaligned_load_store.vgtest new file mode 100644 index 0000000000..1941be79ba --- /dev/null +++ b/none/tests/mips32/unaligned_load_store.vgtest @@ -0,0 +1,2 @@ +prog: unaligned_load_store +vgopts: -q diff --git a/none/tests/mips64/Makefile.am b/none/tests/mips64/Makefile.am index c65b716383..7492e1c742 100644 --- a/none/tests/mips64/Makefile.am +++ b/none/tests/mips64/Makefile.am @@ -37,7 +37,9 @@ EXTRA_DIST = \ test_block_size.stdout.exp test_block_size.stderr.exp \ test_block_size.vgtest \ unaligned_load.stdout.exp-BE unaligned_load.stdout.exp-LE \ - unaligned_load.stderr.exp unaligned_load.vgtest + unaligned_load.stderr.exp unaligned_load.vgtest \ + unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \ + unaligned_load_store.stderr.exp unaligned_load_store.vgtest check_PROGRAMS = \ allexec \ @@ -58,7 +60,8 @@ check_PROGRAMS = \ round \ shift_instructions \ test_block_size \ - unaligned_load + unaligned_load \ + unaligned_load_store AM_CFLAGS += @FLAG_M64@ AM_CXXFLAGS += @FLAG_M64@ diff --git a/none/tests/mips64/unaligned_load_store.c b/none/tests/mips64/unaligned_load_store.c new file mode 100644 index 0000000000..ac6af1f95d --- /dev/null +++ b/none/tests/mips64/unaligned_load_store.c @@ -0,0 +1,67 @@ +#include +unsigned int mem[] = { + 0xaabbccdd, 0x11223344, 0x01823194, 0x01823a08, + 0x00000000, 0x77ff528c, 0x77deb460, 0x00000001 +}; + +void printMem(char* s) +{ + int i; + printf("%s\n", s); + for (i=0; i<7 ; i=i+1) + printf("mem[%d]: 0x%x\n", i, mem[i]); +} + +int main () +{ + printMem("PRE lwl"); + __asm__ volatile("move $a0, %0" "\n\t" + "lw $t0, 0($a0)" "\n\t" + "lwl $t0, 4($a0)" "\n\t" + "sw $t0, 8($a0)" "\n\t" + "lw $t1, 0($a0)" "\n\t" + "lwl $t1, 5($a0)" "\n\t" + "sw $t1, 12($a0)" "\n\t" + "lw $t2, 0($a0)" "\n\t" + "lwl $t2, 6($a0)" "\n\t" + "sw $t2, 16($a0)" "\n\t" + "lw $t3, 0($a0)" "\n\t" + "lwl $t3, 7($a0)" "\n\t" + "sw $t3, 20($a0)" "\n\t" + : + : "r" (mem) + : "a0", "t0", "t1", "t2", "t3", "cc", "memory" + ); + printMem("POST lwl"); + + mem[0] = 0xaabbccdd; + mem[1] = 0x11223344; + mem[2] = 0x01823194; + mem[3] = 0x01823a08; + mem[4] = 0x00000000; + mem[5] = 0x77ff528c; + mem[6] = 0x77deb460; + mem[7] = 0x00000001; + + printMem("PRE lwr"); + __asm__ volatile("move $a0, %0" "\n\t" + "lw $t0, 0($a0)" "\n\t" + "lwr $t0, 4($a0)" "\n\t" + "sw $t0, 8($a0)" "\n\t" + "lw $t1, 0($a0)" "\n\t" + "lwr $t1, 5($a0)" "\n\t" + "sw $t1, 12($a0)" "\n\t" + "lw $t2, 0($a0)" "\n\t" + "lwr $t2, 6($a0)" "\n\t" + "sw $t2, 16($a0)" "\n\t" + "lw $t3, 0($a0)" "\n\t" + "lwr $t3, 7($a0)" "\n\t" + "sw $t3, 20($a0)" "\n\t" + : + : "r" (mem) + : "a0", "t0", "t1", "t2", "t3", "cc", "memory" + ); + printMem("POST lwr"); + + return 0; +} diff --git a/none/tests/mips64/unaligned_load_store.stderr.exp b/none/tests/mips64/unaligned_load_store.stderr.exp new file mode 100644 index 0000000000..e69de29bb2 diff --git a/none/tests/mips64/unaligned_load_store.stdout.exp-BE b/none/tests/mips64/unaligned_load_store.stdout.exp-BE new file mode 100644 index 0000000000..d8c6fee51c --- /dev/null +++ b/none/tests/mips64/unaligned_load_store.stdout.exp-BE @@ -0,0 +1,32 @@ +PRE lwl +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x1823194 +mem[3]: 0x1823a08 +mem[4]: 0x0 +mem[5]: 0x77ff528c +mem[6]: 0x77deb460 +POST lwl +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x11223344 +mem[3]: 0x223344dd +mem[4]: 0x3344ccdd +mem[5]: 0x44bbccdd +mem[6]: 0x77deb460 +PRE lwr +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x1823194 +mem[3]: 0x1823a08 +mem[4]: 0x0 +mem[5]: 0x77ff528c +mem[6]: 0x77deb460 +POST lwr +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0xaabbcc11 +mem[3]: 0xaabb1122 +mem[4]: 0xaa112233 +mem[5]: 0x11223344 +mem[6]: 0x77deb460 diff --git a/none/tests/mips64/unaligned_load_store.stdout.exp-LE b/none/tests/mips64/unaligned_load_store.stdout.exp-LE new file mode 100644 index 0000000000..fbf3b40528 --- /dev/null +++ b/none/tests/mips64/unaligned_load_store.stdout.exp-LE @@ -0,0 +1,32 @@ +PRE lwl +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x1823194 +mem[3]: 0x1823a08 +mem[4]: 0x0 +mem[5]: 0x77ff528c +mem[6]: 0x77deb460 +POST lwl +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x44bbccdd +mem[3]: 0x3344ccdd +mem[4]: 0x223344dd +mem[5]: 0x11223344 +mem[6]: 0x77deb460 +PRE lwr +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x1823194 +mem[3]: 0x1823a08 +mem[4]: 0x0 +mem[5]: 0x77ff528c +mem[6]: 0x77deb460 +POST lwr +mem[0]: 0xaabbccdd +mem[1]: 0x11223344 +mem[2]: 0x11223344 +mem[3]: 0xaa112233 +mem[4]: 0xaabb1122 +mem[5]: 0xaabbcc11 +mem[6]: 0x77deb460 diff --git a/none/tests/mips64/unaligned_load_store.vgtest b/none/tests/mips64/unaligned_load_store.vgtest new file mode 100644 index 0000000000..1941be79ba --- /dev/null +++ b/none/tests/mips64/unaligned_load_store.vgtest @@ -0,0 +1,2 @@ +prog: unaligned_load_store +vgopts: -q