From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Fri, 7 May 2021 10:36:54 +0000 (+0100)
Subject: aarch64: PR target/99037 Fix RTL represntation in move_lo_quad patterns
X-Git-Tag: releases/gcc-8.5.0~11
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=64b6b1d1bc796a7fea189a4c4b0e290540f51ae3;p=thirdparty%2Fgcc.git

aarch64: PR target/99037 Fix RTL represntation in move_lo_quad patterns

This patch fixes the RTL representation of the move_lo_quad patterns to use aarch64_simd_or_scalar_imm_zero
for the zero part rather than a vec_duplicate of zero or a const_int 0.
The expander that generates them is also adjusted so that we use and match the correct const_vector forms throughout.

Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
gcc/ChangeLog:

	PR target/99037
	PR target/100441
	* config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): Use
	aarch64_simd_or_scalar_imm_zero to match zeroes.  Remove pattern
	matching const_int 0.
	(move_lo_quad_internal_be_<mode>): Likewise.
	(move_lo_quad_<mode>): Update for the above.
	* config/aarch64/iterators.md (VQ_2E): Delete.

gcc/testsuite/ChangeLog:

	PR target/99808
	* gcc.target/aarch64/pr99808.c: New test.
---

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 8fe7ba9e2587..c63d4de63194 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1357,10 +1357,10 @@
 ;; On big-endian this is { zeroes, operand }
 
 (define_insn "move_lo_quad_internal_<mode>"
-  [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w")
-	(vec_concat:VQ_NO2E
+  [(set (match_operand:VQ 0 "register_operand" "=w,w,w")
+	(vec_concat:VQ
 	  (match_operand:<VHALF> 1 "register_operand" "w,r,r")
-	  (vec_duplicate:<VHALF> (const_int 0))))]
+	  (match_operand:<VHALF> 2 "aarch64_simd_or_scalar_imm_zero")))]
   "TARGET_SIMD && !BYTES_BIG_ENDIAN"
   "@
    dup\\t%d0, %1.d[0]
@@ -1372,42 +1372,10 @@
    (set_attr "length" "4")]
 )
 
-(define_insn "move_lo_quad_internal_<mode>"
-  [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w")
-	(vec_concat:VQ_2E
-	  (match_operand:<VHALF> 1 "register_operand" "w,r,r")
-	  (const_int 0)))]
-  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
-  "@
-   dup\\t%d0, %1.d[0]
-   fmov\\t%d0, %1
-   dup\\t%d0, %1"
-  [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
-   (set_attr "simd" "yes,*,yes")
-   (set_attr "fp" "*,yes,*")
-   (set_attr "length" "4")]
-)
-
-(define_insn "move_lo_quad_internal_be_<mode>"
-  [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w")
-	(vec_concat:VQ_NO2E
-	  (vec_duplicate:<VHALF> (const_int 0))
-	  (match_operand:<VHALF> 1 "register_operand" "w,r,r")))]
-  "TARGET_SIMD && BYTES_BIG_ENDIAN"
-  "@
-   dup\\t%d0, %1.d[0]
-   fmov\\t%d0, %1
-   dup\\t%d0, %1"
-  [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
-   (set_attr "simd" "yes,*,yes")
-   (set_attr "fp" "*,yes,*")
-   (set_attr "length" "4")]
-)
-
 (define_insn "move_lo_quad_internal_be_<mode>"
-  [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w")
-	(vec_concat:VQ_2E
-	  (const_int 0)
+  [(set (match_operand:VQ 0 "register_operand" "=w,w,w")
+	(vec_concat:VQ
+	  (match_operand:<VHALF> 2 "aarch64_simd_or_scalar_imm_zero")
 	  (match_operand:<VHALF> 1 "register_operand" "w,r,r")))]
   "TARGET_SIMD && BYTES_BIG_ENDIAN"
   "@
@@ -1422,13 +1390,14 @@
 
 (define_expand "move_lo_quad_<mode>"
   [(match_operand:VQ 0 "register_operand")
-   (match_operand:VQ 1 "register_operand")]
+   (match_operand:<VHALF> 1 "register_operand")]
   "TARGET_SIMD"
 {
+  rtx zs = CONST0_RTX (<VHALF>mode);
   if (BYTES_BIG_ENDIAN)
-    emit_insn (gen_move_lo_quad_internal_be_<mode> (operands[0], operands[1]));
+    emit_insn (gen_move_lo_quad_internal_be_<mode> (operands[0], operands[1], zs));
   else
-    emit_insn (gen_move_lo_quad_internal_<mode> (operands[0], operands[1]));
+    emit_insn (gen_move_lo_quad_internal_<mode> (operands[0], operands[1], zs));
   DONE;
 }
 )
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index b7c7dab3aa8f..d2140cff1fb0 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -87,9 +87,6 @@
 ;; VQ without 2 element modes.
 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
 
-;; Quad vector with only 2 element modes.
-(define_mode_iterator VQ_2E [V2DI V2DF])
-
 ;; This mode iterator allows :P to be used for patterns that operate on
 ;; addresses in different modes.  In LP64, only DI will match, while in
 ;; ILP32, either can match.
diff --git a/gcc/testsuite/gcc.target/aarch64/pr99808.c b/gcc/testsuite/gcc.target/aarch64/pr99808.c
new file mode 100644
index 000000000000..4d7edab5c37e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr99808.c
@@ -0,0 +1,14 @@
+/* PR target/99808 */
+/* PR target/99037 */
+/* { dg-do compile } */
+/* { dg-options "-Og -fweb -fno-forward-propagate -g" } */
+
+#include <arm_neon.h>
+
+float32x4_t
+foo (void)
+{
+  float64x2_t arg2 = vcombine_f64 ((float64x1_t) 0UL, (float64x1_t) 1UL);
+  return vcvt_high_f32_f64 ((float32x2_t) 1UL, arg2);
+}
+