From: Robin Dapp <rdapp@ventanamicro.com>
Date: Fri, 12 May 2023 08:26:51 +0000 (+0200)
Subject: RISC-V: Allow more loading of const vectors.
X-Git-Tag: basepoints/gcc-15~9144
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=64d6a4dfd983377c6a91f1711ead71dc59aaefac;p=thirdparty%2Fgcc.git

RISC-V: Allow more loading of const vectors.

This patch fixes the recent vmv patch in order to allow loading
of constants via vmv.vi with the "fixed-vlmax" vectorization flavor.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_const_insns): Remove else.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: New test.
	* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: New test.
---

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 235be758c03c..8320069f92f8 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1295,7 +1295,7 @@ riscv_const_insns (rtx x)
 	   The Wc0, Wc1 constraints are already covered by the
 	   vi constraint so we do not need to check them here
 	   separately.  */
-	else if (TARGET_VECTOR && satisfies_constraint_vi (x))
+	if (TARGET_VECTOR && satisfies_constraint_vi (x))
 	  return 1;
 
 	/* TODO: We may support more const vector in the future.  */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
new file mode 100644
index 000000000000..631ea3bf268e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */
+
+#include "vmv-imm-template.h"
+
+/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
new file mode 100644
index 000000000000..7ded6cc18d24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */
+
+#include "vmv-imm-template.h"
+
+/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */