From: Palmer Dabbelt <palmer@rivosinc.com>
Date: Mon, 11 Nov 2024 15:35:09 +0000 (-0800)
Subject: Merge patch series "Zacas/Zabha support and qspinlocks"
X-Git-Tag: v6.13-rc1~56^2~2
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=64f7b77f0bd9271861ed9e410e9856b6b0b21c48;p=thirdparty%2Fkernel%2Fstable.git

Merge patch series "Zacas/Zabha support and qspinlocks"

Alexandre Ghiti <alexghiti@rivosinc.com> says:

This implements [cmp]xchgXX() macros using Zacas and Zabha extensions
and finally uses those newly introduced macros to add support for
qspinlocks: note that this implementation of qspinlocks satisfies the
forward progress guarantee.

It also uses Ziccrse to provide the qspinlock implementation.

Thanks to Guo and Leonardo for their work!

* b4-shazam-merge: (1314 commits)
  riscv: Add qspinlock support
  dt-bindings: riscv: Add Ziccrse ISA extension description
  riscv: Add ISA extension parsing for Ziccrse
  asm-generic: ticket-lock: Add separate ticket-lock.h
  asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock
  riscv: Implement xchg8/16() using Zabha
  riscv: Implement arch_cmpxchg128() using Zacas
  riscv: Improve zacas fully-ordered cmpxchg()
  riscv: Implement cmpxchg8/16() using Zabha
  dt-bindings: riscv: Add Zabha ISA extension description
  riscv: Implement cmpxchg32/64() using Zacas
  riscv: Do not fail to build on byte/halfword operations with Zawrs
  riscv: Move cpufeature.h macros into their own header

Link: https://lore.kernel.org/r/20241103145153.105097-1-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---

64f7b77f0bd9271861ed9e410e9856b6b0b21c48
diff --cc arch/riscv/include/asm/cpufeature.h
index 04d7ab9eafe08,87ed88fc950da..4bd054c54c21a
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@@ -8,10 -8,11 +8,12 @@@
  
  #include <linux/bitmap.h>
  #include <linux/jump_label.h>
 +#include <linux/workqueue.h>
+ #include <linux/kconfig.h>
+ #include <linux/percpu-defs.h>
+ #include <linux/threads.h>
  #include <asm/hwcap.h>
- #include <asm/alternative-macros.h>
- #include <asm/errno.h>
+ #include <asm/cpufeature-macros.h>
  
  /*
   * These are probed via a device_initcall(), via either the SBI or directly
diff --cc arch/riscv/include/asm/hwcap.h
index 8608883da4539,0aa3c3f5e682b..08d2a5697466d
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -93,9 -93,8 +93,11 @@@
  #define RISCV_ISA_EXT_ZCMOP		84
  #define RISCV_ISA_EXT_ZAWRS		85
  #define RISCV_ISA_EXT_SVVPTC		86
 -#define RISCV_ISA_EXT_ZABHA		87
 -#define RISCV_ISA_EXT_ZICCRSE		88
 +#define RISCV_ISA_EXT_SMMPM		87
 +#define RISCV_ISA_EXT_SMNPM		88
 +#define RISCV_ISA_EXT_SSNPM		89
++#define RISCV_ISA_EXT_ZABHA		90
++#define RISCV_ISA_EXT_ZICCRSE		91
  
  #define RISCV_ISA_EXT_XLINUXENVCFG	127