From: Matthew Stewart Date: Wed, 11 Mar 2026 19:16:00 +0000 (-0400) Subject: drm/amd/display: Hardcode dtbclk value in bw_params X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=64fd3f93a85051d765d04efa59c13f03fdc9d286;p=thirdparty%2Fkernel%2Fstable.git drm/amd/display: Hardcode dtbclk value in bw_params [why&how] dtbclk should always be 600MHz. Previous logic was to get the real value from SMU, but this returns 0 when dtbclk is off. Not a problem during boot when pre-OS enables dtbclk, but PnP was broken due to this. Reviewed-by: Charlene Liu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Matthew Stewart Signed-off-by: Chuanyu Tseng Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 5671fe481d15..b4c6522e922c 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -594,10 +594,7 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr); clk_mgr_base->clks.ref_dtbclk_khz = clk_mgr_base->boot_snapshot.dtbclk * 10; - if (clk_mgr_base->boot_snapshot.dtbclk > 59000) { - /*dtbclk enabled based on*/ - clk_mgr_base->clks.dtbclk_en = true; - } + clk_mgr_base->clks.dtbclk_en = clk_mgr_base->boot_snapshot.dtbclk > 59000; } static struct clk_bw_params dcn42_bw_params = { @@ -1069,7 +1066,7 @@ static void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int) clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled; /* DTBCLK*/ - clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = clk_mgr_base->clks.ref_dtbclk_khz / 1000; + clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = 600; /* Fixed on platform */ clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1; } }