From: Jeff Law <jlaw@ventanamicro.com>
Date: Sun, 27 Aug 2023 18:52:38 +0000 (-0600)
Subject: RISC-V: Fix spill-12 test
X-Git-Tag: basepoints/gcc-15~6634
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6567837fd823a93f7f7948a73ff9dc1153592e8c;p=thirdparty%2Fgcc.git

RISC-V: Fix spill-12 test

Jivan's recent work on IRA results in more efficient code for this test. This
adjusts the expected output for the removal of 5 instructions and conversion of
an addi into a simple mv.

gcc/testsuite
	* gcc.target/riscv/rvv/base/spill-12.c: Update expected output.
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
index de6e0604a3cd..7e83cb7b7c1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
@@ -15,12 +15,7 @@ void fn3 (char*);
 **	addi\tt0,t0,192
 **	add\tsp,sp,t0
 **	...
-**	li\ta0,-8192
-**	addi\ta0,a0,192
-**	li\ta5,8192
-**	addi\ta5,a5,-192
-**	add\ta5,a5,a0
-**	add\ta0,a5,sp
+**	mv\ta0,sp
 **	...
 **	tail\t__riscv_restore_0
 */