From: Andreas Arnez <arnez@linux.ibm.com>
Date: Tue, 2 Oct 2018 11:47:50 +0000 (+0200)
Subject: s390x: Add models "z14" and "z14 ZR1"
X-Git-Tag: VALGRIND_3_16_0~265
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=65d8e9ed96287235b33dfe40525a442dc978e3af;p=thirdparty%2Fvalgrind.git

s390x: Add models "z14" and "z14 ZR1"

Add IBM z14 and IBM z14 ZR1 to the list of known machine models.  Add an
expected output variant for z14 to the s390x-specific "ecag" test case.
In README.s390, refer to a current version of the z/Architecture
Principles of Operation that describes the instructions introduced with
IBM z14.
---

diff --git a/README.s390 b/README.s390
index 4679bb3171..ac9485a625 100644
--- a/README.s390
+++ b/README.s390
@@ -12,7 +12,6 @@ Limitations
 - 31-bit client programs are not supported.
 - Hexadecimal floating point is not supported.
 - Transactional memory is not supported.
-- Instructions operating on vector registers are not supported.
 - memcheck, cachegrind, drd, helgrind, massif, lackey, and none are
   supported. 
 - On machine models predating z10, cachegrind will assume a z10 cache
@@ -49,6 +48,6 @@ Reading Material
 (1) Linux for zSeries ELF ABI Supplement
     http://refspecs.linuxfoundation.org/ELF/zSeries/index.html
 (2) z/Architecture Principles of Operation
-    http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr010.pdf
+    http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr011.pdf
 (3) z/Architecture Reference Summary
-    http://publibfi.boulder.ibm.com/epubs/pdf/dz9zs008.pdf
+    http://publibfi.boulder.ibm.com/epubs/pdf/dz9zs009.pdf
diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index ac3006d691..97c0bacd67 100644
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -1719,6 +1719,8 @@ static const HChar* show_hwcaps_s390x ( UInt hwcaps )
       { VEX_HWCAPS_S390X_FPEXT, "fpext" },
       { VEX_HWCAPS_S390X_LSC,   "lsc" },
       { VEX_HWCAPS_S390X_PFPO,  "pfpo" },
+      { VEX_HWCAPS_S390X_VX,    "vx" },
+      { VEX_HWCAPS_S390X_MSA5,  "msa5" },
    };
    /* Allocate a large enough buffer */
    static HChar buf[sizeof prefix + 
diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index 1e112f5097..37afd185a7 100644
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -144,7 +144,9 @@ typedef
 #define VEX_S390X_MODEL_ZBC12    11
 #define VEX_S390X_MODEL_Z13      12
 #define VEX_S390X_MODEL_Z13S     13
-#define VEX_S390X_MODEL_UNKNOWN  14     /* always last in list */
+#define VEX_S390X_MODEL_Z14      14
+#define VEX_S390X_MODEL_Z14_ZR1  15
+#define VEX_S390X_MODEL_UNKNOWN  16     /* always last in list */
 #define VEX_S390X_MODEL_MASK     0x3F
 
 #define VEX_HWCAPS_S390X_LDISP (1<<6)   /* Long-displacement facility */
diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
index 56a28d108d..cbb88472da 100644
--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
@@ -578,6 +578,8 @@ static UInt VG_(get_machine_model)(void)
       { "2828", VEX_S390X_MODEL_ZBC12 },
       { "2964", VEX_S390X_MODEL_Z13 },
       { "2965", VEX_S390X_MODEL_Z13S },
+      { "3906", VEX_S390X_MODEL_Z14 },
+      { "3907", VEX_S390X_MODEL_Z14_ZR1 },
    };
 
    Int    model, n, fh;
diff --git a/none/tests/s390x/ecag.stdout.exp-z14 b/none/tests/s390x/ecag.stdout.exp-z14
new file mode 100644
index 0000000000..98f53280c3
--- /dev/null
+++ b/none/tests/s390x/ecag.stdout.exp-z14
@@ -0,0 +1,28 @@
+L1 topology: separate data and instruction; private
+L1 cache line size data: 256
+L1 cache line size insn: 256
+L1 total cachesize data: 131072
+L1 total cachesize insn: 131072
+L1 set. assoc.     data: 8
+L1 set. assoc.     insn: 8
+L2 topology: separate data and instruction; private
+L2 cache line size data: 256
+L2 cache line size insn: 256
+L2 total cachesize data: 4194304
+L2 total cachesize insn: 2097152
+L2 set. assoc.     data: 8
+L2 set. assoc.     insn: 8
+L3 topology: unified data and instruction; shared
+L3 cache line size data: 256
+L3 cache line size insn: 256
+L3 total cachesize data: 134217728
+L3 total cachesize insn: 134217728
+L3 set. assoc.     data: 32
+L3 set. assoc.     insn: 32
+L4 topology: unified data and instruction; shared
+L4 cache line size data: 256
+L4 cache line size insn: 256
+L4 total cachesize data: 704643072
+L4 total cachesize insn: 704643072
+L4 set. assoc.     data: 42
+L4 set. assoc.     insn: 42
diff --git a/tests/s390x_features.c b/tests/s390x_features.c
index 25734abb1c..301785faca 100644
--- a/tests/s390x_features.c
+++ b/tests/s390x_features.c
@@ -98,6 +98,8 @@ model_info models[] = {
    { "2828", "zBC12"  },
    { "2964", "z13"    },
    { "2965", "z13s"   },
+   { "3906", "z14"    },
+   { "3907", "z14 ZR1"},
 };