From: Matthew Gerlach Date: Fri, 21 Feb 2025 17:04:51 +0000 (-0600) Subject: dt-bindings: PCI: altera: Add binding for Agilex X-Git-Tag: v6.15-rc1~119^2~15^2~1 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6843f38e16b96b072d0f576bf7cddde8cc5a103a;p=thirdparty%2Fkernel%2Flinux.git dt-bindings: PCI: altera: Add binding for Agilex Add the compatible bindings for the three variants of the Agilex PCIe Hard IP. Signed-off-by: Matthew Gerlach Reviewed-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20250221170452.875419-2-matthew.gerlach@linux.intel.com [kwilczynski: update description within devicetree bindings] Signed-off-by: Krzysztof Wilczyński --- diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml index 52533fccc134a..5d3f48a001b71 100644 --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml @@ -12,9 +12,19 @@ maintainers: properties: compatible: + description: Each family of socfpga has its own implementation of the + PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5 + family of chips. The Stratix10 family of chips is supported by the + altr,pcie-root-port-2.0. The Agilex family of chips has three, + non-register compatible, variants of PCIe Hard IP referred to as the + F-Tile, P-Tile, and R-Tile, depending on the specific chip instance. + enum: - altr,pcie-root-port-1.0 - altr,pcie-root-port-2.0 + - altr,pcie-root-port-3.0-f-tile + - altr,pcie-root-port-3.0-p-tile + - altr,pcie-root-port-3.0-r-tile reg: items: