From: Paolo Abeni Date: Tue, 17 Mar 2026 12:32:35 +0000 (+0100) Subject: Merge branch 'initial-support-for-pic64-hpsc-hx-ethernet-endpoint' X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=68e8619d221400f094490644dce9d3a4efffb6c5;p=thirdparty%2Flinux.git Merge branch 'initial-support-for-pic64-hpsc-hx-ethernet-endpoint' Charles Perry says: ==================== Initial support for PIC64-HPSC/HX Ethernet endpoint This series add basic support for Microchip "PIC64-HPSC" and "PIC64HX" Ethernet endpoint. Both SoCs contain 4 GEM IP with support for MII/RGMII/SGMII/USXGMII at rates of 10M to 10G. Only RGMII and SGMII at a rate of 1G is tested for now. Each GEM IP has 8 priority queues and the revision register reads 0x220c010e. One particularity of this instantiation of GEM is that the MDIO controller within the GEM IP is disconnected from any physical pin and the SoC rely on another standalone MDIO controller. The maximum jumbo frame size also seems to be different on PIC64-HPSC/HX (16383) than what most other platforms use (10240). I've found that I need to tweak a bit the MTU calculation for this, otherwise the RXBS field of the DMACFG register overflows. See patch 2 for more details. PIC64-HPSC/HX also supports other features guarded behind CAPS bit like MACB_CAPS_QBV but I've omitted those intentionally because I didn't test these. ==================== Link: https://patch.msgid.link/20260313140610.3681752-1-charles.perry@microchip.com Signed-off-by: Paolo Abeni --- 68e8619d221400f094490644dce9d3a4efffb6c5