From: Uros Bizjak Date: Wed, 3 Oct 2018 21:49:11 +0000 (+0200) Subject: backport: i386.h (SSE_REGNO): Fix check for FIRST_REX_SSE_REG. X-Git-Tag: releases/gcc-7.4.0~132 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6927df526d03b070cfe63b0e0f97ac20151eb55c;p=thirdparty%2Fgcc.git backport: i386.h (SSE_REGNO): Fix check for FIRST_REX_SSE_REG. Backport from mainline 2018-09-28 Uros Bizjak * config/i386/i386.h (SSE_REGNO): Fix check for FIRST_REX_SSE_REG. (GET_SSE_REGNO): Rename from SSE_REGNO. Update all uses for rename. From-SVN: r264826 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f742a977ca34..e84f4936fad1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2018-10-03 Uros Bizjak + + Backport from mainline + 2018-09-28 Uros Bizjak + + * config/i386/i386.h (SSE_REGNO): Fix check for FIRST_REX_SSE_REG. + (GET_SSE_REGNO): Rename from SSE_REGNO. Update all uses for rename. + 2018-10-03 Jonathan Wakely PR other/87353 @@ -1076,8 +1084,8 @@ 2017-09-13 Kugan Vivekanandarajah * config/aarch64/aarch64.c (aarch64_override_options_after_change_1): - Disable pc relative literal load irrespective of TARGET_FIX_ERR_A53_84341 - for default. + Disable pc relative literal load irrespective of + TARGET_FIX_ERR_A53_84341 for default. 2018-03-06 Denis Chertykov diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index f398c1f6c3ff..f3aa1a7c32c8 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -9442,7 +9442,7 @@ construct_container (machine_mode mode, machine_mode orig_mode, case X86_64_SSEDF_CLASS: if (mode != BLKmode) return gen_reg_or_parallel (mode, orig_mode, - SSE_REGNO (sse_regno)); + GET_SSE_REGNO (sse_regno)); break; case X86_64_X87_CLASS: case X86_64_COMPLEX_X87_CLASS: @@ -9458,7 +9458,7 @@ construct_container (machine_mode mode, machine_mode orig_mode, && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode) return gen_reg_or_parallel (mode, orig_mode, - SSE_REGNO (sse_regno)); + GET_SSE_REGNO (sse_regno)); if (n == 4 && regclass[0] == X86_64_SSE_CLASS && regclass[1] == X86_64_SSEUP_CLASS @@ -9466,7 +9466,7 @@ construct_container (machine_mode mode, machine_mode orig_mode, && regclass[3] == X86_64_SSEUP_CLASS && mode != BLKmode) return gen_reg_or_parallel (mode, orig_mode, - SSE_REGNO (sse_regno)); + GET_SSE_REGNO (sse_regno)); if (n == 8 && regclass[0] == X86_64_SSE_CLASS && regclass[1] == X86_64_SSEUP_CLASS @@ -9478,7 +9478,7 @@ construct_container (machine_mode mode, machine_mode orig_mode, && regclass[7] == X86_64_SSEUP_CLASS && mode != BLKmode) return gen_reg_or_parallel (mode, orig_mode, - SSE_REGNO (sse_regno)); + GET_SSE_REGNO (sse_regno)); if (n == 2 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS) @@ -9524,7 +9524,7 @@ construct_container (machine_mode mode, machine_mode orig_mode, exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (SFmode, - SSE_REGNO (sse_regno)), + GET_SSE_REGNO (sse_regno)), GEN_INT (i*8)); sse_regno++; break; @@ -9532,7 +9532,7 @@ construct_container (machine_mode mode, machine_mode orig_mode, exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (DFmode, - SSE_REGNO (sse_regno)), + GET_SSE_REGNO (sse_regno)), GEN_INT (i*8)); sse_regno++; break; @@ -9578,7 +9578,7 @@ construct_container (machine_mode mode, machine_mode orig_mode, exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (tmpmode, - SSE_REGNO (sse_regno)), + GET_SSE_REGNO (sse_regno)), GEN_INT (pos*8)); sse_regno++; break; @@ -11013,7 +11013,7 @@ setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum) set_mem_alias_set (mem, set); set_mem_align (mem, GET_MODE_ALIGNMENT (smode)); - emit_move_insn (mem, gen_rtx_REG (smode, SSE_REGNO (i))); + emit_move_insn (mem, gen_rtx_REG (smode, GET_SSE_REGNO (i))); } emit_label (label); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 32a01d030731..16396fc250bd 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1557,10 +1557,10 @@ enum reg_class #define FIRST_FLOAT_REG FIRST_STACK_REG #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) -#define SSE_REGNO(N) \ - ((N) < 8 ? FIRST_SSE_REG + (N) \ - : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \ - : (FIRST_EXT_REX_SSE_REG + (N) - 16)) +#define GET_SSE_REGNO(N) \ + ((N) < 8 ? FIRST_SSE_REG + (N) \ + : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \ + : FIRST_EXT_REX_SSE_REG + (N) - 16) /* The class value for index registers, and the one for base regs. */ diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 77e97e17f1a3..7d9e601fc623 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1499,7 +1499,7 @@ if (GET_CODE (elt) != SET || GET_CODE (SET_DEST (elt)) != REG || GET_MODE (SET_DEST (elt)) != V8SImode - || REGNO (SET_DEST (elt)) != SSE_REGNO (i) + || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i) || SET_SRC (elt) != CONST0_RTX (V8SImode)) return false; } diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c8c3a5045b76..9c72e6f8b1d3 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17245,7 +17245,7 @@ for (regno = 0; regno < nregs; regno++) XVECEXP (operands[0], 0, regno + 1) - = gen_rtx_SET (gen_rtx_REG (V8SImode, SSE_REGNO (regno)), + = gen_rtx_SET (gen_rtx_REG (V8SImode, GET_SSE_REGNO (regno)), CONST0_RTX (V8SImode)); })