From: Greg Kroah-Hartman Date: Tue, 3 Feb 2026 14:29:36 +0000 (+0100) Subject: 6.1-stable patches X-Git-Tag: v5.10.249~40 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6a4ee848037ad2b74ea252274ccc1f3ac2e0a02a;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch drm-amdgpu-soc21-fix-xclk-for-apus.patch scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch --- diff --git a/queue-6.1/drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch b/queue-6.1/drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch new file mode 100644 index 0000000000..3a430858cd --- /dev/null +++ b/queue-6.1/drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch @@ -0,0 +1,37 @@ +From cc4f433b14e05eaa4a98fd677b836e9229422387 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 28 Jan 2026 20:51:08 -0500 +Subject: drm/amdgpu/gfx10: fix wptr reset in KGQ init +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit cc4f433b14e05eaa4a98fd677b836e9229422387 upstream. + +wptr is a 64 bit value and we need to update the +full value, not just 32 bits. Align with what we +already do for KCQs. + +Reviewed-by: Timur Kristóf +Reviewed-by: Jesse Zhang +Signed-off-by: Alex Deucher +(cherry picked from commit e80b1d1aa1073230b6c25a1a72e88f37e425ccda) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -6584,7 +6584,7 @@ static int gfx_v10_0_gfx_init_queue(stru + memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); + /* reset the ring */ + ring->wptr = 0; +- *ring->wptr_cpu_addr = 0; ++ atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); + amdgpu_ring_clear_ring(ring); + #ifdef BRING_UP_DEBUG + mutex_lock(&adev->srbm_mutex); diff --git a/queue-6.1/drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch b/queue-6.1/drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch new file mode 100644 index 0000000000..42000a4b81 --- /dev/null +++ b/queue-6.1/drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch @@ -0,0 +1,37 @@ +From b1f810471c6a6bd349f7f9f2f2fed96082056d46 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 28 Jan 2026 18:09:03 -0500 +Subject: drm/amdgpu/gfx11: fix wptr reset in KGQ init +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit b1f810471c6a6bd349f7f9f2f2fed96082056d46 upstream. + +wptr is a 64 bit value and we need to update the +full value, not just 32 bits. Align with what we +already do for KCQs. + +Reviewed-by: Timur Kristóf +Reviewed-by: Jesse Zhang +Signed-off-by: Alex Deucher +(cherry picked from commit 1f16866bdb1daed7a80ca79ae2837a9832a74fbc) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -3716,7 +3716,7 @@ static int gfx_v11_0_gfx_init_queue(stru + memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); + /* reset the ring */ + ring->wptr = 0; +- *ring->wptr_cpu_addr = 0; ++ atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); + amdgpu_ring_clear_ring(ring); + #ifdef BRING_UP_DEBUG + mutex_lock(&adev->srbm_mutex); diff --git a/queue-6.1/drm-amdgpu-soc21-fix-xclk-for-apus.patch b/queue-6.1/drm-amdgpu-soc21-fix-xclk-for-apus.patch new file mode 100644 index 0000000000..2058b2da69 --- /dev/null +++ b/queue-6.1/drm-amdgpu-soc21-fix-xclk-for-apus.patch @@ -0,0 +1,39 @@ +From e7fbff9e7622a00c2b53cb14df481916f0019742 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 16 Jan 2026 17:33:05 -0500 +Subject: drm/amdgpu/soc21: fix xclk for APUs + +From: Alex Deucher + +commit e7fbff9e7622a00c2b53cb14df481916f0019742 upstream. + +The reference clock is supposed to be 100Mhz, but it +appears to actually be slightly lower (99.81Mhz). + +Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14451 +Reviewed-by: Jesse Zhang +Signed-off-by: Alex Deucher +(cherry picked from commit 637fee3954d4bd509ea9d95ad1780fc174489860) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -202,7 +202,13 @@ static u32 soc21_get_config_memsize(stru + + static u32 soc21_get_xclk(struct amdgpu_device *adev) + { +- return adev->clock.spll.reference_freq; ++ u32 reference_clock = adev->clock.spll.reference_freq; ++ ++ /* reference clock is actually 99.81 Mhz rather than 100 Mhz */ ++ if ((adev->flags & AMD_IS_APU) && reference_clock == 10000) ++ return 9981; ++ ++ return reference_clock; + } + + diff --git a/queue-6.1/pinctrl-lpass-lpi-implement-.get_direction-for-the-gpio-driver.patch b/queue-6.1/pinctrl-lpass-lpi-implement-.get_direction-for-the-gpio-driver.patch deleted file mode 100644 index f82fb943bf..0000000000 --- a/queue-6.1/pinctrl-lpass-lpi-implement-.get_direction-for-the-gpio-driver.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 4f0d22ec60cee420125f4055af76caa0f373a3fe Mon Sep 17 00:00:00 2001 -From: Bartosz Golaszewski -Date: Mon, 26 Jan 2026 14:56:27 +0100 -Subject: pinctrl: lpass-lpi: implement .get_direction() for the GPIO driver - -From: Bartosz Golaszewski - -commit 4f0d22ec60cee420125f4055af76caa0f373a3fe upstream. - -GPIO controller driver should typically implement the .get_direction() -callback as GPIOLIB internals may try to use it to determine the state -of a pin. Add it for the LPASS LPI driver. - -Reported-by: Abel Vesa -Cc: stable@vger.kernel.org -Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") -Signed-off-by: Bartosz Golaszewski -Reviewed-by: Konrad Dybcio -Tested-by: Konrad Dybcio # X1E CRD -Tested-by: Abel Vesa -Signed-off-by: Linus Walleij -Signed-off-by: Greg Kroah-Hartman ---- - drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c -+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c -@@ -248,6 +248,22 @@ static const struct pinconf_ops lpi_gpio - .pin_config_group_set = lpi_config_set, - }; - -+static int lpi_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) -+{ -+ unsigned long config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, 0); -+ struct lpi_pinctrl *state = gpiochip_get_data(chip); -+ unsigned long arg; -+ int ret; -+ -+ ret = lpi_config_get(state->ctrl, pin, &config); -+ if (ret) -+ return ret; -+ -+ arg = pinconf_to_config_argument(config); -+ -+ return arg ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; -+} -+ - static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) - { - struct lpi_pinctrl *state = gpiochip_get_data(chip); -@@ -346,6 +362,7 @@ static void lpi_gpio_dbg_show(struct seq - #endif - - static const struct gpio_chip lpi_gpio_template = { -+ .get_direction = lpi_gpio_get_direction, - .direction_input = lpi_gpio_direction_input, - .direction_output = lpi_gpio_direction_output, - .get = lpi_gpio_get, diff --git a/queue-6.1/scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch b/queue-6.1/scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch new file mode 100644 index 0000000000..010b0549ce --- /dev/null +++ b/queue-6.1/scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch @@ -0,0 +1,37 @@ +From 5157c328edb35bac05ce77da473c3209d20e0bbb Mon Sep 17 00:00:00 2001 +From: Tamir Duberstein +Date: Wed, 23 Jul 2025 11:39:40 -0400 +Subject: scripts: generate_rust_analyzer: Add compiler_builtins -> core dep + +From: Tamir Duberstein + +commit 5157c328edb35bac05ce77da473c3209d20e0bbb upstream. + +Add a dependency edge from `compiler_builtins` to `core` to +`scripts/generate_rust_analyzer.py` to match `rust/Makefile`. This has +been incorrect since commit 8c4555ccc55c ("scripts: add +`generate_rust_analyzer.py`") + +Signed-off-by: Tamir Duberstein +Reviewed-by: Jesung Yang +Acked-by: Benno Lossin +Fixes: 8c4555ccc55c ("scripts: add `generate_rust_analyzer.py`") +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/20250723-rust-analyzer-pin-init-v1-1-3c6956173c78@kernel.org +Signed-off-by: Miguel Ojeda +Signed-off-by: Greg Kroah-Hartman +--- + scripts/generate_rust_analyzer.py | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/scripts/generate_rust_analyzer.py ++++ b/scripts/generate_rust_analyzer.py +@@ -73,7 +73,7 @@ def generate_crates(srctree, objtree, sy + append_crate( + "compiler_builtins", + srctree / "rust" / "compiler_builtins.rs", +- [], ++ ["core"], + ) + + append_crate( diff --git a/queue-6.1/series b/queue-6.1/series index 18a1c4388b..f96155b6b2 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -203,7 +203,6 @@ scsi-firewire-sbp-target-fix-overflow-in-sbp_make_tp.patch asoc-intel-sof_es8336-fix-headphone-gpio-logic-inver.patch gpiolib-acpi-use-bit_ull-for-u64-mask-in-address-spa.patch dma-pool-distinguish-between-missing-and-exhausted-a.patch -pinctrl-lpass-lpi-implement-.get_direction-for-the-gpio-driver.patch pinctrl-meson-mark-the-gpio-controller-as-sleeping.patch riscv-compat-fix-compat_uts_machine-definition.patch asoc-fsl-imx-card-do-not-force-slot-width-to-sample-width.patch @@ -213,3 +212,7 @@ scsi-qla2xxx-edif-fix-dma_free_coherent-size.patch efivarfs-fix-error-propagation-in-efivar_entry_get.patch mptcp-only-reset-subflow-errors-when-propagated.patch flex_proportions-make-fprop_new_period-hardirq-safe.patch +scripts-generate_rust_analyzer-add-compiler_builtins-core-dep.patch +drm-amdgpu-soc21-fix-xclk-for-apus.patch +drm-amdgpu-gfx10-fix-wptr-reset-in-kgq-init.patch +drm-amdgpu-gfx11-fix-wptr-reset-in-kgq-init.patch