From: Uros Bizjak Date: Thu, 28 Nov 2013 18:14:23 +0000 (+0100) Subject: backport: re PR target/56788 (_mm_frcz_sd and _mm_frcz_ss ignore their second argument) X-Git-Tag: releases/gcc-4.7.4~382 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6b1ca0e2304db1dd8bcbc0c14da63e25b4589dc7;p=thirdparty%2Fgcc.git backport: re PR target/56788 (_mm_frcz_sd and _mm_frcz_ss ignore their second argument) Backport from mainline 2013-11-23 Uros Bizjak PR target/56788 * config/i386/i386.c (bdesc_multi_arg) : Declare as MULTI_ARG_1_SF instruction. : Decleare as MULTI_ARG_1_DF instruction. * config/i386/sse.md (*xop_vmfrcz2): Rename from *xop_vmfrcz_. * config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss to merge scalar result with __A. (_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar result with __A. testsuite/ChangeLog: Backport from mainline 2013-11-27 Uros Bizjak Ganesh Gopalasubramanian PR target/56788 * gcc.target/i386/xop-frczX.c: New test. From-SVN: r205497 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 524a9ff2b035..0374bb83d022 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2013-11-28 Uros Bizjak + + Backport from mainline + 2013-11-23 Uros Bizjak + + PR target/56788 + * config/i386/i386.c (bdesc_multi_arg) : + Declare as MULTI_ARG_1_SF instruction. + : Decleare as MULTI_ARG_1_DF instruction. + * config/i386/sse.md (*xop_vmfrcz2): Rename + from *xop_vmfrcz_. + * config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss + to merge scalar result with __A. + (_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar + result with __A. + 2013-11-19 Uros Bizjak Backport from mainline diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index a30c3f6e5feb..c74dba0506ac 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -27206,8 +27206,8 @@ static const struct builtin_description bdesc_multi_arg[] = { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 }, diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 492cf21cd065..6e3ec008eb1a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -11456,7 +11456,6 @@ [(set_attr "type" "ssecvt1") (set_attr "mode" "")]) -;; scalar insns (define_expand "xop_vmfrcz2" [(set (match_operand:VF_128 0 "register_operand") (vec_merge:VF_128 @@ -11466,11 +11465,9 @@ (match_dup 3) (const_int 1)))] "TARGET_XOP" -{ - operands[3] = CONST0_RTX (mode); -}) + "operands[3] = CONST0_RTX (mode);") -(define_insn "*xop_vmfrcz_" +(define_insn "*xop_vmfrcz2" [(set (match_operand:VF_128 0 "register_operand" "=x") (vec_merge:VF_128 (unspec:VF_128 diff --git a/gcc/config/i386/xopintrin.h b/gcc/config/i386/xopintrin.h index 3ebcb4b9f485..49aeed19d808 100644 --- a/gcc/config/i386/xopintrin.h +++ b/gcc/config/i386/xopintrin.h @@ -745,13 +745,17 @@ _mm_frcz_pd (__m128d __A) extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_frcz_ss (__m128 __A, __m128 __B) { - return (__m128) __builtin_ia32_vfrczss ((__v4sf)__A, (__v4sf)__B); + return (__m128) __builtin_ia32_movss ((__v4sf)__A, + (__v4sf) + __builtin_ia32_vfrczss ((__v4sf)__B)); } extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_frcz_sd (__m128d __A, __m128d __B) { - return (__m128d) __builtin_ia32_vfrczsd ((__v2df)__A, (__v2df)__B); + return (__m128d) __builtin_ia32_movsd ((__v2df)__A, + (__v2df) + __builtin_ia32_vfrczsd ((__v2df)__B)); } extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5ae1e57a1f11..09ff06ffb554 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2013-11-28 Uros Bizjak + + Backport from mainline + 2013-11-27 Uros Bizjak + Ganesh Gopalasubramanian + + PR target/56788 + * gcc.target/i386/xop-frczX.c: New test. + 2013-11-25 Vidya Praveen Backport from mainline diff --git a/gcc/testsuite/gcc.target/i386/xop-frczX.c b/gcc/testsuite/gcc.target/i386/xop-frczX.c new file mode 100644 index 000000000000..931b5ce397bf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-frczX.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include + +void +check_mm_vmfrcz_sd (__m128d __A, __m128d __B) +{ + union128d a, b, c; + double d[2]; + + a.x = __A; + b.x = __B; + c.x = _mm_frcz_sd (__A, __B); + d[0] = b.a[0] - (int)b.a[0] ; + d[1] = a.a[1]; + if (check_union128d (c, d)) + abort (); +} + +void +check_mm_vmfrcz_ss (__m128 __A, __m128 __B) +{ + union128 a, b, c; + float f[4]; + + a.x = __A; + b.x = __B; + c.x = _mm_frcz_ss (__A, __B); + f[0] = b.a[0] - (int)b.a[0] ; + f[1] = a.a[1]; + f[2] = a.a[2]; + f[3] = a.a[3]; + if (check_union128 (c, f)) + abort (); +} + +static void +xop_test (void) +{ + union128 a, b; + union128d c,d; + int i; + + for (i = 0; i < 4; i++) + { + a.a[i] = i + 3.5; + b.a[i] = i + 7.9; + } + for (i = 0; i < 2; i++) + { + c.a[i] = i + 3.5; + d.a[i] = i + 7.987654321; + } + check_mm_vmfrcz_ss (a.x, b.x); + check_mm_vmfrcz_sd (c.x, d.x); +}