From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date: Mon, 24 Oct 2022 02:03:12 +0000 (+0800)
Subject: RISC-V: Support (set (mem) (const_poly_int))
X-Git-Tag: basepoints/gcc-14~3756
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6bfea64164c3f1989d34656ab96d03a7cda2143e;p=thirdparty%2Fgcc.git

RISC-V: Support (set (mem) (const_poly_int))

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)).
---

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a39047dd76..53a91a1003b9 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1958,6 +1958,18 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
 {
   if (CONST_POLY_INT_P (src))
     {
+      /*
+	Handle:
+	  (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
+		  (const_int 96 [0x60])) [0  S1 A8])
+	  (const_poly_int:QI [8, 8]))
+	"../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
+      */
+      if (MEM_P (dest))
+	{
+	  emit_move_insn (dest, force_reg (mode, src));
+	  return true;
+	}
       poly_int64 value = rtx_to_poly_int64 (src);
       if (!value.is_constant () && !TARGET_VECTOR)
 	{