From: Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Date: Fri, 11 Oct 2013 18:53:52 +0000 (+0000)
Subject: vsx.md (*vsx_le_perm_load_v2di): Generalize to handle vector float as well.
X-Git-Tag: releases/gcc-4.9.0~3560
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6e8b7d9cd6c483e85dc243ac4edf561ca7d8f7ef;p=thirdparty%2Fgcc.git

vsx.md (*vsx_le_perm_load_v2di): Generalize to handle vector float as well.

2013-10-11  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to
	handle vector float as well.
	(*vsx_le_perm_load_v4si): Likewise.
	(*vsx_le_perm_store_v2di): Likewise.
	(*vsx_le_perm_store_v4si): Likewise.

From-SVN: r203458
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5a6fff651cf8..41e29dc534d1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2013-10-11  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	* config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to
+	handle vector float as well.
+	(*vsx_le_perm_load_v4si): Likewise.
+	(*vsx_le_perm_store_v2di): Likewise.
+	(*vsx_le_perm_store_v4si): Likewise.
+
 2013-10-11  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
 
 	* config/rs6000/vector.md (vec_realign_load<mode>): Generate vperm
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 517fac66be35..dfb9ab197839 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -219,18 +219,18 @@
 
 ;; The patterns for LE permuted loads and stores come before the general
 ;; VSX moves so they match first.
-(define_insn_and_split "*vsx_le_perm_load_v2di"
-  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
-        (match_operand:V2DI 1 "memory_operand" "Z"))]
+(define_insn_and_split "*vsx_le_perm_load_<mode>"
+  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
+        (match_operand:VSX_D 1 "memory_operand" "Z"))]
   "!BYTES_BIG_ENDIAN && TARGET_VSX"
   "#"
   "!BYTES_BIG_ENDIAN && TARGET_VSX"
   [(set (match_dup 2)
-        (vec_select:V2DI
+        (vec_select:<MODE>
           (match_dup 1)
           (parallel [(const_int 1) (const_int 0)])))
    (set (match_dup 0)
-        (vec_select:V2DI
+        (vec_select:<MODE>
           (match_dup 2)
           (parallel [(const_int 1) (const_int 0)])))]
   "
@@ -242,19 +242,19 @@
   [(set_attr "type" "vecload")
    (set_attr "length" "8")])
 
-(define_insn_and_split "*vsx_le_perm_load_v4si"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
-        (match_operand:V4SI 1 "memory_operand" "Z"))]
+(define_insn_and_split "*vsx_le_perm_load_<mode>"
+  [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
+        (match_operand:VSX_W 1 "memory_operand" "Z"))]
   "!BYTES_BIG_ENDIAN && TARGET_VSX"
   "#"
   "!BYTES_BIG_ENDIAN && TARGET_VSX"
   [(set (match_dup 2)
-        (vec_select:V4SI
+        (vec_select:<MODE>
           (match_dup 1)
           (parallel [(const_int 2) (const_int 3)
                      (const_int 0) (const_int 1)])))
    (set (match_dup 0)
-        (vec_select:V4SI
+        (vec_select:<MODE>
           (match_dup 2)
           (parallel [(const_int 2) (const_int 3)
                      (const_int 0) (const_int 1)])))]
@@ -333,18 +333,18 @@
   [(set_attr "type" "vecload")
    (set_attr "length" "8")])
 
-(define_insn_and_split "*vsx_le_perm_store_v2di"
-  [(set (match_operand:V2DI 0 "memory_operand" "=Z")
-        (match_operand:V2DI 1 "vsx_register_operand" "+wa"))]
+(define_insn_and_split "*vsx_le_perm_store_<mode>"
+  [(set (match_operand:VSX_D 0 "memory_operand" "=Z")
+        (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))]
   "!BYTES_BIG_ENDIAN && TARGET_VSX"
   "#"
   "!BYTES_BIG_ENDIAN && TARGET_VSX"
   [(set (match_dup 2)
-        (vec_select:V2DI
+        (vec_select:<MODE>
           (match_dup 1)
           (parallel [(const_int 1) (const_int 0)])))
    (set (match_dup 0)
-        (vec_select:V2DI
+        (vec_select:<MODE>
           (match_dup 2)
           (parallel [(const_int 1) (const_int 0)])))]
   "
@@ -356,19 +356,19 @@
   [(set_attr "type" "vecstore")
    (set_attr "length" "8")])
 
-(define_insn_and_split "*vsx_le_perm_store_v4si"
-  [(set (match_operand:V4SI 0 "memory_operand" "=Z")
-        (match_operand:V4SI 1 "vsx_register_operand" "+wa"))]
+(define_insn_and_split "*vsx_le_perm_store_<mode>"
+  [(set (match_operand:VSX_W 0 "memory_operand" "=Z")
+        (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))]
   "!BYTES_BIG_ENDIAN && TARGET_VSX"
   "#"
   "!BYTES_BIG_ENDIAN && TARGET_VSX"
   [(set (match_dup 2)
-        (vec_select:V4SI
+        (vec_select:<MODE>
           (match_dup 1)
           (parallel [(const_int 2) (const_int 3)
 	             (const_int 0) (const_int 1)])))
    (set (match_dup 0)
-        (vec_select:V4SI
+        (vec_select:<MODE>
           (match_dup 2)
           (parallel [(const_int 2) (const_int 3)
 	             (const_int 0) (const_int 1)])))]