From: H.J. Lu <hjl.tools@gmail.com>
Date: Sun, 1 Aug 2021 16:55:33 +0000 (-0700)
Subject: i386: Improve SImode constant - __builtin_clzll for -mno-lzcnt
X-Git-Tag: basepoints/gcc-13~5657
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6f0c43e97825ee54e3779afbedcd0def12443001;p=thirdparty%2Fgcc.git

i386: Improve SImode constant - __builtin_clzll for -mno-lzcnt

Add a zero_extend patten for bsr_rex64_1 and use it to split SImode
constant - __builtin_clzll to avoid unncessary zero_extend.

gcc/

	PR target/78103
	* config/i386/i386.md (bsr_rex64_1_zext): New.
	(combine splitter for constant - clzll): Replace gen_bsr_rex64_1
	with gen_bsr_rex64_1_zext.

gcc/testsuite/

	PR target/78103
	* gcc.target/i386/pr78103-2.c: Also scan incl.
	* gcc.target/i386/pr78103-3.c: Scan leal|addl|incl for x32.  Also
	scan incq.
---

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index c9787d73262a..0c23ddb8d1f4 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -14796,6 +14796,21 @@
    (set_attr "znver1_decode" "vector")
    (set_attr "mode" "DI")])
 
+(define_insn "bsr_rex64_1_zext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI
+	  (minus:SI (const_int 63)
+		    (subreg:SI
+		      (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))
+		      0))))
+   (clobber (reg:CC FLAGS_REG))]
+  "!TARGET_LZCNT && TARGET_64BIT"
+  "bsr{q}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "znver1_decode" "vector")
+   (set_attr "mode" "DI")])
+
 (define_insn "bsr"
   [(set (reg:CCZ FLAGS_REG)
 	(compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
@@ -14907,7 +14922,7 @@
   operands[5] = lowpart_subreg (SImode, operands[3], DImode);
   if (INTVAL (operands[2]) == 63)
     {
-      emit_insn (gen_bsr_rex64_1 (operands[3], operands[1]));
+      emit_insn (gen_bsr_rex64_1_zext (operands[3], operands[1]));
       emit_move_insn (operands[0], operands[5]);
       DONE;
     }
diff --git a/gcc/testsuite/gcc.target/i386/pr78103-2.c b/gcc/testsuite/gcc.target/i386/pr78103-2.c
index b35233829261..30f7f98f60a4 100644
--- a/gcc/testsuite/gcc.target/i386/pr78103-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr78103-2.c
@@ -4,7 +4,7 @@
 /* { dg-final { scan-assembler-not {\mmovl\M} } } */
 /* { dg-final { scan-assembler-not {\mxor[lq]\M} } } */
 /* { dg-final { scan-assembler-not {\msubl\M} } } */
-/* { dg-final { scan-assembler {\m(leal|addl)\M} } } */
+/* { dg-final { scan-assembler {\m(leal|addl|incl)\M} } } */
 
 unsigned int
 foo (unsigned int x)
diff --git a/gcc/testsuite/gcc.target/i386/pr78103-3.c b/gcc/testsuite/gcc.target/i386/pr78103-3.c
index 49a36eccf4d1..b8d82312a0ed 100644
--- a/gcc/testsuite/gcc.target/i386/pr78103-3.c
+++ b/gcc/testsuite/gcc.target/i386/pr78103-3.c
@@ -5,7 +5,8 @@
 /* { dg-final { scan-assembler-not {\mmovslq\M} } } */
 /* { dg-final { scan-assembler-not {\mxor[lq]\M} } } */
 /* { dg-final { scan-assembler-not {\msubq\M} } } */
-/* { dg-final { scan-assembler {\m(leaq|addq)\M} } } */
+/* { dg-final { scan-assembler {\m(leaq|addq|incq)\M} { target { ! x32 } } } } */
+/* { dg-final { scan-assembler {\m(leal|addl|incl)\M} { target x32 } } } */
 
 unsigned long long
 foo (unsigned int x)