From: Julian Seward <jseward@acm.org>
Date: Sun, 19 Sep 2004 11:55:46 +0000 (+0000)
Subject: x86 -> IR -> x86: fix enough bits to make OOo 1.1.2 work.
X-Git-Tag: svn/VALGRIND_3_0_1^2~1063
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6fb849f3b2865905c17d41502fa30e9591988186;p=thirdparty%2Fvalgrind.git

x86 -> IR -> x86: fix enough bits to make OOo 1.1.2 work.


git-svn-id: svn://svn.valgrind.org/vex/trunk@271
---

diff --git a/VEX/priv/guest-x86/toIR.c b/VEX/priv/guest-x86/toIR.c
index 398b126911..3751f73cb4 100644
--- a/VEX/priv/guest-x86/toIR.c
+++ b/VEX/priv/guest-x86/toIR.c
@@ -3930,6 +3930,10 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, UInt delta )
                fp_do_op_ST_ST ( "mul", Iop_MulF64, 0, modrm - 0xC8, False );
                break;
 
+            case 0xE0 ... 0xE7: /* FSUBR %st(0),%st(?) */
+               fp_do_oprev_ST_ST ( "subr", Iop_SubF64, 0, modrm - 0xE0, False );
+               break;
+
             case 0xE8 ... 0xEF: /* FSUB %st(0),%st(?) */
                fp_do_op_ST_ST ( "sub", Iop_SubF64, 0, modrm - 0xE8, False );
                break;
@@ -7345,13 +7349,9 @@ static UInt disInstr ( UInt delta, Bool* isEnd )
          putIReg(4, R_EAX, unop(Iop_16Sto32, getIReg(2, R_EAX)));
          DIP("cwde\n");
       } else {
-         vassert(0);
-//--          vg_assert(sz == 2);
-//--          uInstr2(cb, GET,   1, ArchReg, R_EAX, TempReg, t1);
-//--          uInstr1(cb, WIDEN, 2, TempReg, t1); /* 2 == dst size */
-//--          uWiden(cb, 1, True);
-//--          uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX);
-//--          DIP("cbw\n");
+         vassert(sz == 2);
+         putIReg(2, R_EAX, unop(Iop_8Sto16, getIReg(1, R_EAX)));
+         DIP("cbw\n");
       }
       break;
 
@@ -8124,7 +8124,7 @@ static UInt disInstr ( UInt delta, Bool* isEnd )
 //--       break;
 //-- 
    case 0xAA: /* STOS, no REP prefix */
-//--    case 0xAB:
+   case 0xAB:
       dis_string_op( dis_STOS, ( opc == 0xAA ? 1 : sz ), "stos", sorb );
       break;
 //--    
diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c
index b02e7db48a..e0812f9538 100644
--- a/VEX/priv/host-x86/isel.c
+++ b/VEX/priv/host-x86/isel.c
@@ -638,21 +638,23 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
       }
 
       switch (e->Iex.Unop.op) {
+         case Iop_8Uto16:
          case Iop_8Uto32:
          case Iop_16Uto32: {
             HReg dst = newVRegI(env);
             HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-            UInt mask = e->Iex.Unop.op==Iop_8Uto32 ? 0xFF : 0xFFFF;
+            UInt mask = e->Iex.Unop.op==Iop_16Uto32 ? 0xFFFF : 0xFF;
             addInstr(env, mk_MOVsd_RR(src,dst) );
             addInstr(env, X86Instr_Alu32R(Xalu_AND,
                                           X86RMI_Imm(mask), dst));
             return dst;
          }
+         case Iop_8Sto16:
          case Iop_8Sto32:
          case Iop_16Sto32: {
             HReg dst = newVRegI(env);
             HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-            UInt amt = e->Iex.Unop.op==Iop_8Sto32 ? 24 : 16;
+            UInt amt = e->Iex.Unop.op==Iop_16Sto32 ? 16 : 24;
             addInstr(env, mk_MOVsd_RR(src,dst) );
             addInstr(env, X86Instr_Sh32(Xsh_SHL, amt, X86RM_Reg(dst)));
             addInstr(env, X86Instr_Sh32(Xsh_SAR, amt, X86RM_Reg(dst)));
diff --git a/VEX/priv/ir/irdefs.c b/VEX/priv/ir/irdefs.c
index 3dd9740dfd..4b4b5838ba 100644
--- a/VEX/priv/ir/irdefs.c
+++ b/VEX/priv/ir/irdefs.c
@@ -635,8 +635,13 @@ void typeOfPrimop ( IROp op, IRType* t_dst, IRType* t_arg1, IRType* t_arg2 )
       case Iop_1Uto8:   UNARY(Ity_I8,Ity_Bit);
       case Iop_1Uto32:  UNARY(Ity_I32,Ity_Bit);
       case Iop_32to1:   UNARY(Ity_Bit,Ity_I32);
+
       case Iop_8Uto32:  UNARY(Ity_I32,Ity_I8);
       case Iop_8Sto32:  UNARY(Ity_I32,Ity_I8);
+
+      case Iop_8Uto16:  UNARY(Ity_I16,Ity_I8);
+      case Iop_8Sto16:  UNARY(Ity_I16,Ity_I8);
+
       case Iop_16Uto32: UNARY(Ity_I32,Ity_I16);
       case Iop_16Sto32: UNARY(Ity_I32,Ity_I16);
       case Iop_32Sto64: UNARY(Ity_I64,Ity_I32);