From: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Date: Tue, 23 Dec 2025 15:26:00 +0000 (+0100)
Subject: arm64: dts: qcom: Minor whitespace cleanup
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=70101cb09c205e260df918ef367d9fe5098c464f;p=thirdparty%2Fkernel%2Flinux.git

arm64: dts: qcom: Minor whitespace cleanup

The DTS code coding style expects exactly one space around '=' and
before '{' characters.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251223152559.155703-4-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---

diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 51f8b3e0749c3..9ef57ad0ca71d 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -1100,119 +1100,119 @@
 			compatible = "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500";
 			reg = <0x0 0x15000000 0x0 0x100000>;
 
-			interrupts =<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
-				    <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
 
 			#iommu-cells = <2>;
 			#global-interrupts = <1>;
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 14d9f31e7086d..a89ad87d998ac 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -5048,7 +5048,7 @@
 					port@1 {
 						reg = <1>;
 
-						mdss0_dsi0_out: endpoint{ };
+						mdss0_dsi0_out: endpoint { };
 					};
 				};