From: Uros Bizjak Date: Thu, 7 Apr 2011 21:50:05 +0000 (+0200) Subject: sse.md (avx_cmps3): Add missing output register constraint. X-Git-Tag: releases/gcc-4.5.3~87 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7212aebc9b71764f0f0f81aa9104c66501a0c9ff;p=thirdparty%2Fgcc.git sse.md (avx_cmps3): Add missing output register constraint. * config/i386/sse.md (avx_cmps3): Add missing output register constraint. (*vec_concatv2sf_avx): Fix wrong register constraint in alternative 3 of operand 1. (*vec_set_0_avx): Avoid combining registers from different units in a single alternative. (*vec_set_0_sse4_1): Ditto. (*vec_set_0_sse2): Ditto. (vec_set_0): Ditto. (sse2_storehpd): Ditto. (sse2_loadhpd): Ditto. (sse4_1_insertps): Use nonimmediate_operand for operand 2. * config/i386/predicates.md (sse_comparison_operator): Do not define as special predicate. From-SVN: r172150 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3611039e1d64..b8d07e93ccf2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2011-04-07 Uros Bizjak + + * config/i386/sse.md (avx_cmps3): Add + missing output register constraint. + (*vec_concatv2sf_avx): Fix wrong register constraint in + alternative 3 of operand 1. + (*vec_set_0_avx): Avoid combining registers from different + units in a single alternative. + (*vec_set_0_sse4_1): Ditto. + (*vec_set_0_sse2): Ditto. + (vec_set_0): Ditto. + (sse2_storehpd): Ditto. + (sse2_loadhpd): Ditto. + (sse4_1_insertps): Use nonimmediate_operand for operand 2. + * config/i386/predicates.md (sse_comparison_operator): Do not + define as special predicate. + 2011-04-07 Jakub Jelinek Backported from mainline diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 83f5e5dac314..cc5dd8a07388 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -990,13 +990,8 @@ ;; Return 1 if OP is a comparison that can be used in the CMPSS/CMPPS insns. ;; The first set are supported directly; the second set can't be done with ;; full IEEE support, i.e. NaNs. -;; -;; ??? It would seem that we have a lot of uses of this predicate that pass -;; it the wrong mode. We got away with this because the old function didn't -;; check the mode at all. Mirror that for now by calling this a special -;; predicate. -(define_special_predicate "sse_comparison_operator" +(define_predicate "sse_comparison_operator" (match_code "eq,lt,le,unordered,ne,unge,ungt,ordered")) ;; Return 1 if OP is a comparison operator that can be issued by diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e85ffd9d68d8..56e5e1b80980 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1484,7 +1484,7 @@ (set_attr "mode" "")]) (define_insn "avx_cmps3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "") + [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") (vec_merge:SSEMODEF2P (unspec:SSEMODEF2P [(match_operand:SSEMODEF2P 1 "register_operand" "x") @@ -3934,7 +3934,7 @@ (define_insn "*vec_concatv2sf_avx" [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,*y ,*y") (vec_concat:V2SF - (match_operand:SF 1 "nonimmediate_operand" " x,x,m, x , m") + (match_operand:SF 1 "nonimmediate_operand" " x,x,m, 0 , m") (match_operand:SF 2 "vector_move_operand" " x,m,C,*ym, C")))] "TARGET_AVX" "@ @@ -4023,13 +4023,15 @@ DONE; }) +;; Avoid combining registers from different units in a single alternative, +;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "*vec_set_0_avx" - [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x, x,x, x,m") + [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x, x,x, x,m, m,m") (vec_merge:SSEMODE4S (vec_duplicate:SSEMODE4S (match_operand: 2 - "general_operand" " x,m,*r,x,*rm,x*rfF")) - (match_operand:SSEMODE4S 1 "vector_move_operand" " C,C, C,x, x,0") + "general_operand" " x,m,*r,x,*rm,x,*r,fF")) + (match_operand:SSEMODE4S 1 "vector_move_operand" " C,C, C,x, x,0, 0,0") (const_int 1)))] "TARGET_AVX" "@ @@ -4038,20 +4040,24 @@ vmovd\t{%2, %0|%0, %2} vmovss\t{%2, %1, %0|%0, %1, %2} vpinsrd\t{$0, %2, %1, %0|%0, %1, %2, 0} + # + # #" - [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,*") - (set_attr "prefix_extra" "*,*,*,*,1,*") - (set_attr "length_immediate" "*,*,*,*,1,*") + [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,*,*,*") + (set_attr "prefix_extra" "*,*,*,*,1,*,*,*") + (set_attr "length_immediate" "*,*,*,*,1,*,*,*") (set_attr "prefix" "vex") - (set_attr "mode" "SF,,SI,SF,TI,*")]) + (set_attr "mode" "SF,,SI,SF,TI,*,*,*")]) +;; Avoid combining registers from different units in a single alternative, +;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "*vec_set_0_sse4_1" - [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x, x,x, x,m") + [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x, x,x, x, m,m") (vec_merge:SSEMODE4S (vec_duplicate:SSEMODE4S (match_operand: 2 - "general_operand" " x,m,*r,x,*rm,*rfF")) - (match_operand:SSEMODE4S 1 "vector_move_operand" " C,C, C,0, 0,0") + "general_operand" " x,m,*r,x,*rm,*r,fF")) + (match_operand:SSEMODE4S 1 "vector_move_operand" " C,C, C,0, 0, 0,0") (const_int 1)))] "TARGET_SSE4_1" "@ @@ -4060,44 +4066,53 @@ movd\t{%2, %0|%0, %2} movss\t{%2, %0|%0, %2} pinsrd\t{$0, %2, %0|%0, %2, 0} + # #" - [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,*") - (set_attr "prefix_extra" "*,*,*,*,1,*") - (set_attr "length_immediate" "*,*,*,*,1,*") - (set_attr "mode" "SF,,SI,SF,TI,*")]) + [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,*,*") + (set_attr "prefix_extra" "*,*,*,*,1,*,*") + (set_attr "length_immediate" "*,*,*,*,1,*,*") + (set_attr "mode" "SF,,SI,SF,TI,*,*")]) +;; Avoid combining registers from different units in a single alternative, +;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "*vec_set_0_sse2" - [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x, x,x,m") + [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x, x,x,m, m,m") (vec_merge:SSEMODE4S (vec_duplicate:SSEMODE4S (match_operand: 2 - "general_operand" " m,*r,x,x*rfF")) - (match_operand:SSEMODE4S 1 "vector_move_operand" " C, C,0,0") + "general_operand" " m,*r,x,x,*r,fF")) + (match_operand:SSEMODE4S 1 "vector_move_operand" " C, C,0,0, 0,0") (const_int 1)))] "TARGET_SSE2" "@ mov\t{%2, %0|%0, %2} movd\t{%2, %0|%0, %2} movss\t{%2, %0|%0, %2} + # + # #" [(set_attr "type" "ssemov") - (set_attr "mode" ",SI,SF,*")]) + (set_attr "mode" ",SI,SF,*,*,*")]) +;; Avoid combining registers from different units in a single alternative, +;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "vec_set_0" - [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x,m") + [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand" "=x,x,m, m,m") (vec_merge:SSEMODE4S (vec_duplicate:SSEMODE4S (match_operand: 2 - "general_operand" " m,x,x*rfF")) - (match_operand:SSEMODE4S 1 "vector_move_operand" " C,0,0") + "general_operand" " m,x,x,*r,fF")) + (match_operand:SSEMODE4S 1 "vector_move_operand" " C,0,0, 0,0") (const_int 1)))] "TARGET_SSE" "@ movss\t{%2, %0|%0, %2} movss\t{%2, %0|%0, %2} + # + # #" [(set_attr "type" "ssemov") - (set_attr "mode" "SF")]) + (set_attr "mode" "SF,SF,*,*,*")]) ;; A subset is vec_setv4sf. (define_insn "*vec_setv4sf_avx" @@ -4152,7 +4167,7 @@ (define_insn "sse4_1_insertps" [(set (match_operand:V4SF 0 "register_operand" "=x") - (unspec:V4SF [(match_operand:V4SF 2 "register_operand" "x") + (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "xm") (match_operand:V4SF 1 "register_operand" "0") (match_operand:SI 3 "const_0_to_255_operand" "n")] UNSPEC_INSERTPS))] @@ -4823,6 +4838,8 @@ (set_attr "prefix" "vex") (set_attr "mode" "V1DF,V2DF,DF,DF,DF")]) +;; Avoid combining registers from different units in a single alternative, +;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "sse2_storehpd" [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r") (vec_select:DF @@ -4926,6 +4943,8 @@ (set_attr "prefix" "vex") (set_attr "mode" "V1DF,V2DF,DF,DF,DF")]) +;; Avoid combining registers from different units in a single alternative, +;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "sse2_loadhpd" [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o,o,o") (vec_concat:V2DF @@ -4999,6 +5018,8 @@ (set_attr "prefix" "vex") (set_attr "mode" "DF,V1DF,V1DF,V1DF,DF,DF,DF")]) +;; Avoid combining registers from different units in a single alternative, +;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "sse2_loadlpd" [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,m,m,m") (vec_concat:V2DF