From: Paolo Bonzini Date: Tue, 23 Dec 2025 14:12:38 +0000 (+0100) Subject: target/i386/tcg: do not mark all SSE instructions as unaligned X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=73dd6e4a36dd8d85548292f382a4d479e2810371;p=thirdparty%2Fqemu.git target/i386/tcg: do not mark all SSE instructions as unaligned If the vex_special field was not initialized, it was considered to be X86_VEX_SSEUnaligned (whose value was zero). Add a new value to fix that. Cc: qemu-stable@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index 9d3a7c0d42..f662364c60 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1068,15 +1068,15 @@ static void decode_0F10(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) { static const X86OpEntry opcodes_0F11_reg[4] = { - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* MOVUPS */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* MOVUPD */ X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex5), X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex5), /* MOVSD */ }; static const X86OpEntry opcodes_0F11_mem[4] = { - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* MOVUPS */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* MOVUPD */ X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex5), X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex5), /* MOVSD */ }; @@ -2624,6 +2624,9 @@ static bool validate_vex(DisasContext *s, X86DecodedInsn *decode) X86OpEntry *e = &decode->e; switch (e->vex_special) { + case X86_VEX_None: + break; + case X86_VEX_REPScalar: /* * Instructions which differ between 00/66 and F2/F3 in the diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index 7f23d373ea..9282296900 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -242,6 +242,8 @@ typedef enum X86InsnSpecial { * section of the manual. */ typedef enum X86VEXSpecial { + X86_VEX_None, + /* Legacy SSE instructions that allow unaligned operands */ X86_VEX_SSEUnaligned,