From: Petar Jovanovic Date: Sat, 27 Sep 2014 05:40:33 +0000 (+0000) Subject: mips64: enable soft-float build of the tests X-Git-Tag: svn/VALGRIND_3_11_0~962 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7449ebb9210adf368d5add23646156f5a4224564;p=thirdparty%2Fvalgrind.git mips64: enable soft-float build of the tests Cavium toolchain defaults to soft-float, so it is important to enable full build of the test suite to work in that case as well. This boils down to protecting FPU-specific code segments with #if defined(__mips_hard_float) #endif git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14572 --- diff --git a/none/tests/mips64/fpu_arithmetic.c b/none/tests/mips64/fpu_arithmetic.c index fa410fe19c..0da6009cd9 100644 --- a/none/tests/mips64/fpu_arithmetic.c +++ b/none/tests/mips64/fpu_arithmetic.c @@ -3,6 +3,7 @@ #include "rounding_mode.h" #include "macro_fpu.h" +#if defined(__mips_hard_float) int arithmeticOperations(flt_art_op_t op) { double fd_d = 0; @@ -154,9 +155,11 @@ int arithmeticOperations(flt_art_op_t op) } return 0; } +#endif int main() { +#if defined(__mips_hard_float) flt_art_op_t op; printf("-------------------------- %s --------------------------\n", @@ -164,6 +167,6 @@ int main() for (op = ABSS; op <= NMSUBD; op++) { arithmeticOperations(op); } - +#endif return 0; } diff --git a/none/tests/mips64/fpu_branches.c b/none/tests/mips64/fpu_branches.c index 5642735a3c..375f54f9cd 100644 --- a/none/tests/mips64/fpu_branches.c +++ b/none/tests/mips64/fpu_branches.c @@ -3,6 +3,7 @@ int main() { +#if defined(__mips_hard_float) int i = 0; printf("--- BC1F --- if fs == ft then " \ @@ -144,6 +145,7 @@ int main() TESTINST_CONDs("c.ngt.s", i); TESTINST_CONDd("c.ngt.d", i); } +#endif return 0; } diff --git a/none/tests/mips64/fpu_control_word.c b/none/tests/mips64/fpu_control_word.c index 4a46621ca1..5451e66489 100644 --- a/none/tests/mips64/fpu_control_word.c +++ b/none/tests/mips64/fpu_control_word.c @@ -1,5 +1,6 @@ #include +#if defined(__mips_hard_float) #define TESTINST_CFC1_CTC1(N) \ { \ unsigned int out = 0; \ @@ -14,6 +15,9 @@ ); \ printf("out=%d, in=%d\n", out, N); \ } +#else +#define TESTINST_CFC1_CTC1(N) +#endif int main() { diff --git a/none/tests/mips64/fpu_load_store.c b/none/tests/mips64/fpu_load_store.c index 124e526035..c1631d2eca 100644 --- a/none/tests/mips64/fpu_load_store.c +++ b/none/tests/mips64/fpu_load_store.c @@ -3,6 +3,7 @@ int main() { +#if defined(__mips_hard_float) int i; int s1 = sizeof(int); int s2 = sizeof(unsigned long long); @@ -64,6 +65,7 @@ int main() for (i = 0; i < (N-1)*s1; i = i+4) { TEST6("swxc1", i); } +#endif return 0; } diff --git a/none/tests/mips64/load_store_unaligned.c b/none/tests/mips64/load_store_unaligned.c index 59e3d3d68d..60c61916b2 100644 --- a/none/tests/mips64/load_store_unaligned.c +++ b/none/tests/mips64/load_store_unaligned.c @@ -23,6 +23,7 @@ unsigned long long memDst[] = { int main() { +#if defined(__mips_hard_float) int i, index; unsigned long long outLoad; for (i = 0; i < N * SOLL; i++) { @@ -42,5 +43,6 @@ int main() printf("i: %d, memSrc[%d]: 0x%llx, memDst[%d]: 0x%llx, outLoad: 0x%llx\n", i, index, memSrc[index], index, memDst[index], outLoad); } +#endif return 0; } diff --git a/none/tests/mips64/macro_fpu.h b/none/tests/mips64/macro_fpu.h index 8c804a54bc..8d98b02bf8 100644 --- a/none/tests/mips64/macro_fpu.h +++ b/none/tests/mips64/macro_fpu.h @@ -52,6 +52,7 @@ const char *flt_round_op_names[] = { "cvt.l.d", "cvt.s.l", }; +#if defined(__mips_hard_float) #define UNOPdd(op) \ fd_d = 0; \ __asm__ __volatile__( \ @@ -352,3 +353,4 @@ const char *flt_round_op_names[] = { printf("%s, bc1f out=%f, fs=%f, ft=%f\n", \ instruction, outd, fs_d[i], ft_d[i]); \ } +#endif diff --git a/none/tests/mips64/move_instructions.c b/none/tests/mips64/move_instructions.c index 647e6fcc3d..da3182af1e 100644 --- a/none/tests/mips64/move_instructions.c +++ b/none/tests/mips64/move_instructions.c @@ -46,6 +46,7 @@ const double fs2_f[] = { -347856.475, 23.04 -1.0, 356047.56 }; +#if defined(__mips_hard_float) #define TEST1(mem) \ { \ unsigned long long out; \ @@ -190,9 +191,11 @@ const double fs2_f[] = { printf("%s :: RDval: 0x%x, RSval: 0x%x, out: 0x%lx\n", \ instruction, RDval, RSval, out); \ } +#endif int main() { +#if defined(__mips_hard_float) int i; init_reg_val2(); @@ -366,6 +369,6 @@ int main() TEST5("movt", 0x5555ffff, 0xffffffff, t3, t1); TEST5("movt", 0xeeeeeeee, 0xffffeeee, t3, t0); } - +#endif return 0; } diff --git a/none/tests/mips64/round.c b/none/tests/mips64/round.c index 5fb0fb4c49..e46c7b6fae 100644 --- a/none/tests/mips64/round.c +++ b/none/tests/mips64/round.c @@ -2,6 +2,7 @@ #include "rounding_mode.h" #include "macro_fpu.h" +#if defined(__mips_hard_float) int directedRoundingMode(flt_dir_op_t op) { int fd_w = 0; long long int fd_l = 0; @@ -170,9 +171,11 @@ int FCSRRoundingMode(flt_round_op_t op1) } return 0; } +#endif int main() { +#if defined(__mips_hard_float) flt_dir_op_t op; flt_round_op_t op1; @@ -187,5 +190,6 @@ int main() for (op1 = CVTDS; op1 <= CVTSL; op1++) { FCSRRoundingMode(op1); } +#endif return 0; } diff --git a/none/tests/mips64/rounding_mode.h b/none/tests/mips64/rounding_mode.h index e47ee19680..38354be9dd 100644 --- a/none/tests/mips64/rounding_mode.h +++ b/none/tests/mips64/rounding_mode.h @@ -1,3 +1,4 @@ +#if defined(__mips_hard_float) typedef enum { TO_NEAREST=0, TO_ZERO, @@ -59,3 +60,4 @@ void set_rounding_mode(round_mode_t mode) break; } } +#endif diff --git a/none/tests/mips64/test_fcsr.c b/none/tests/mips64/test_fcsr.c index ef92f7b71e..742bb83388 100644 --- a/none/tests/mips64/test_fcsr.c +++ b/none/tests/mips64/test_fcsr.c @@ -2,6 +2,7 @@ int main () { +#if defined(__mips_hard_float) long out [] = {0, 0}; __asm__ volatile("cfc1 $a1, $31" "\n\t" "dli $t0, 0x405ee0a3d70a3d71" "\n\t" @@ -22,5 +23,6 @@ int main () : "a1", "a2", "t0", "$f0" ); printf("FCSR::1: 0x%lx, 2: 0x%lx\n", out[0], out[1]); +#endif return 0; }