From: bui duc phuc Date: Tue, 2 Jun 2026 10:16:05 +0000 (+0700) Subject: ASoC: rockchip: spdif: Reorder clock enable sequence X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=74d3f01a90ca0e49cf4b1980e7b0a07bcf18f064;p=thirdparty%2Flinux.git ASoC: rockchip: spdif: Reorder clock enable sequence Enable the 'hclk' bus clock before the 'mclk' controller clock during runtime resume. The bus clock provides the register access interface, so enable it before the controller clock. This also makes the resume sequence the reverse of the suspend sequence, which keeps the clock ordering consistent. Signed-off-by: bui duc phuc Link: https://patch.msgid.link/20260602101608.45137-3-phucduc.bui@gmail.com Signed-off-by: Mark Brown --- diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c index 581624f2682ef..8de5b76cfe791 100644 --- a/sound/soc/rockchip/rockchip_spdif.c +++ b/sound/soc/rockchip/rockchip_spdif.c @@ -76,16 +76,16 @@ static int rk_spdif_runtime_resume(struct device *dev) struct rk_spdif_dev *spdif = dev_get_drvdata(dev); int ret; - ret = clk_prepare_enable(spdif->mclk); + ret = clk_prepare_enable(spdif->hclk); if (ret) { - dev_err(spdif->dev, "mclk clock enable failed %d\n", ret); + dev_err(spdif->dev, "hclk clock enable failed %d\n", ret); return ret; } - ret = clk_prepare_enable(spdif->hclk); + ret = clk_prepare_enable(spdif->mclk); if (ret) { - clk_disable_unprepare(spdif->mclk); - dev_err(spdif->dev, "hclk clock enable failed %d\n", ret); + clk_disable_unprepare(spdif->hclk); + dev_err(spdif->dev, "mclk clock enable failed %d\n", ret); return ret; }