From: Greg Kroah-Hartman Date: Fri, 16 Jan 2026 15:51:56 +0000 (+0100) Subject: 6.6-stable patches X-Git-Tag: v6.6.121~7 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=768901ab8c2ea2764ae4cdc309b6ff17b0fef3bc;p=thirdparty%2Fkernel%2Fstable-queue.git 6.6-stable patches added patches: riscv-replace-function-like-macro-by-static-inline-function.patch --- diff --git a/queue-6.6/riscv-replace-function-like-macro-by-static-inline-function.patch b/queue-6.6/riscv-replace-function-like-macro-by-static-inline-function.patch new file mode 100644 index 0000000000..dce4a1f613 --- /dev/null +++ b/queue-6.6/riscv-replace-function-like-macro-by-static-inline-function.patch @@ -0,0 +1,60 @@ +From 121f34341d396b666d8a90b24768b40e08ca0d61 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= +Date: Sat, 19 Apr 2025 13:13:59 +0200 +Subject: riscv: Replace function-like macro by static inline function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Björn Töpel + +commit 121f34341d396b666d8a90b24768b40e08ca0d61 upstream. + +The flush_icache_range() function is implemented as a "function-like +macro with unused parameters", which can result in "unused variables" +warnings. + +Replace the macro with a static inline function, as advised by +Documentation/process/coding-style.rst. + +Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable") +Signed-off-by: Björn Töpel +Link: https://lore.kernel.org/r/20250419111402.1660267-1-bjorn@kernel.org +Signed-off-by: Palmer Dabbelt +Signed-off-by: Ron Economos +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/include/asm/cacheflush.h | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -34,11 +34,6 @@ static inline void flush_dcache_page(str + flush_dcache_folio(page_folio(page)); + } + +-/* +- * RISC-V doesn't have an instruction to flush parts of the instruction cache, +- * so instead we just flush the whole thing. +- */ +-#define flush_icache_range(start, end) flush_icache_all() + #define flush_icache_user_page(vma, pg, addr, len) \ + flush_icache_mm(vma->vm_mm, 0) + +@@ -59,6 +54,16 @@ void flush_icache_mm(struct mm_struct *m + + #endif /* CONFIG_SMP */ + ++/* ++ * RISC-V doesn't have an instruction to flush parts of the instruction cache, ++ * so instead we just flush the whole thing. ++ */ ++#define flush_icache_range flush_icache_range ++static inline void flush_icache_range(unsigned long start, unsigned long end) ++{ ++ flush_icache_all(); ++} ++ + extern unsigned int riscv_cbom_block_size; + extern unsigned int riscv_cboz_block_size; + void riscv_init_cbo_blocksizes(void); diff --git a/queue-6.6/series b/queue-6.6/series index a7395f504d..b3a7ccc7c8 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -86,3 +86,4 @@ asoc-fsl_sai-add-missing-registers-to-cache-default.patch scsi-sg-fix-occasional-bogus-elapsed-time-that-excee.patch bpf-test_run-fix-ctx-leak-in-bpf_prog_test_run_xdp-error-path.patch gpio-pca953x-fix-wrong-error-probe-return-value.patch +riscv-replace-function-like-macro-by-static-inline-function.patch